Method for forming a MFMIS memory device

A memory device comprising:

• a first source/drain region and a second source/drain region overlying the first source/drain region;
• a first gate electrode and a semiconductor layer vertically between the first and second source/drain regions, wherein the first gate electrode is electrically floating;
• a gate dielectric layer laterally between and bordering the first gate electrode and the semiconductor layer, wherein the first gate electrode, the semiconductor and gate dielectric layers, and the first and second source/drain regions define a common sidewall;
• a ferroelectric layer lining the common sidewall;
• and
• a second gate electrode bordering the ferroelectric layer on an opposite side of the ferroelectric layer as the common sidewall.

A memory device comprising:

• a first source/drain region and a second source/drain region overlying the first source/drain region;
• an internal gate electrode and a semiconductor channel that overlie the first source/drain region and that underlie the second source/drain region;
• a gate dielectric layer between and bordering the internal gate electrode and the semiconductor channel;
• a control gate electrode on an opposite side of the internal gate electrode as the semiconductor channel;
• and
• a ferroelectric layer between and bordering the control and internal gate electrodes;
• wherein the control gate electrode and the internal gate electrode are laterally spaced in a first direction, and wherein a width of the control gate electrode in a second direction transverse to the first direction is less than that of the internal gate electrode.