Memory device

A memory device, comprising:

• a substrate comprising an array region and a staircase region;
• a multi-layer stack disposed on the substrate in the array region, wherein the multi-layer stack comprises a plurality of conductive layers and a plurality of dielectric layers stacked alternately, and the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure, wherein the staircase structure has a plurality of steps, one of the plurality of steps comprises at least two conductive layers and at least two dielectric layers, and the at least two conductive layers has a sidewall aligned with a sidewall of the at least two dielectric layers;
• and
• a plurality of conductive contacts standing on the plurality of steps of the staircase structure, wherein at least one conductive contact extends downwardly into a corresponding step of the staircase structure, so that the at least two conductive layers are electrically connected to each other through the at least one conductive contact.

A memory device, comprising:

• a substrate comprising an array region and a staircase region;
• a multi-layer stack disposed on the substrate in the array region, wherein the multi-layer stack comprises a plurality of conductive layers and a plurality of dielectric layers stacked alternately, and the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure;
• a first conformal layer covering at least one step of the staircase structure;
• a second conformal layer covering at least two steps of the staircase structure;
• a third conformal layer covering at least four steps of the staircase structure, wherein the first, second, and third conformal layers are electrically isolated from each other.