Three-dimensional ferroelectric random-access memory (FeRAM)

A process for fabricating a memory structure above a planar surface of a substrate, comprising:

• forming a bottom isolation layer on the planar surface;
• forming and patterning an etch stop layer above the bottom isolation layer;
• forming a predetermined number of alternating layers of intermediate isolation material and a first dielectric material;
• cutting a plurality of shafts from the top of the alternating layers of the intermediate isolation material and the first dielectric material down to the etch stop layer;
• recessing each of the layers of the first dielectric material to create a first plurality of pockets;
• filling each of the pockets with a first semiconductor material of a first conductivity type;
• forming conformally a gate oxide layer over the sidewalls of the shafts, the gate oxide material being in contact with the first semiconductor material in the pockets along the sidewalls of the shafts;
• forming conformally a ferroelectric layer over the gate oxide layer;
• filling the shafts of a conductive gate material to form a gate electrode;
• forming a plurality of slots through the alternating layers of intermediate isolation material and the first dielectric material between the filled shafts;
• recessing the first dielectric material exposed along the sidewalls of the slots to form a second plurality of pockets and exposing in each pocket at least a portion of the first semiconductor material;
• and
• forming conformally a second semiconductor material of a second conductivity type on the inside walls of the second plurality of pockets.