G11C 7/1045
Read-write mode select circuits
Official title: {Read-write mode select circuits}
G11C7/1045 (Read-write mode select circuits) appears on 1,850 US grants and 1,575 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,850
- Published applications
- 1,575
- Assignees
- 262
- Inventors
- 2,247
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 3 | 0 |
| 1987 | 1 | 0 |
| 1988 | 3 | 0 |
| 1989 | 2 | 0 |
| 1990 | 0 | 0 |
| 1991 | 6 | 0 |
| 1992 | 4 | 0 |
| 1993 | 4 | 0 |
| 1994 | 3 | 0 |
| 1995 | 6 | 0 |
| 1996 | 14 | 0 |
| 1997 | 28 | 0 |
| 1998 | 46 | 0 |
| 1999 | 38 | 0 |
| 2000 | 88 | 0 |
| 2001 | 68 | 32 |
| 2002 | 72 | 75 |
| 2003 | 56 | 65 |
| 2004 | 67 | 54 |
| 2005 | 58 | 80 |
| 2006 | 73 | 74 |
| 2007 | 55 | 71 |
| 2008 | 56 | 75 |
| 2009 | 65 | 70 |
| 2010 | 65 | 57 |
| 2011 | 58 | 37 |
| 2012 | 66 | 51 |
| 2013 | 43 | 46 |
| 2014 | 44 | 29 |
| 2015 | 32 | 33 |
| 2016 | 41 | 39 |
| 2017 | 48 | 48 |
| 2018 | 52 | 42 |
| 2019 | 60 | 92 |
| 2020 | 89 | 92 |
| 2021 | 87 | 100 |
| 2022 | 100 | 98 |
| 2023 | 102 | 77 |
| 2024 | 70 | 63 |
| 2025 | 57 | 41 |
| 2026 | 18 | 34 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Non-volatile programmable logic device based on multi-chip package15 Sep 2026US 12,737,520 B2iCometrue Company Ltd.
- Local internal discovery and configuration of individually selected and jointly selected devices1 Sep 2026US 12,724,729 B2Rambus Inc.
- Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption16 Jun 2026US 12,658,231 B2Samsung Electronics Co., Ltd.
- Command address input buffer bias current reduction2 Jun 2026US 12,645,399 B2
- Flexible configuration of memory module data width26 May 2026US 12,639,219 B2Intel Corporation
- Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption17 Sep 2026US 2026/0279420 A1Samsung Electronics Co., Ltd.
- Command address input buffer bias current reduction10 Sep 2026US 2026/0267562 A1Lodestar Licensing Group LLC
- Non-volatile memory device having high i/o efficiency based on separate command address protocol, operation method thereof, and storage device including same20 Aug 2026US 2026/0244366 A1Samsung Electronics Co., Ltd.
- Multi-channel memory16 Jul 2026US 2026/0204303 A1SK hynix Inc.
- Systems and methods for dual standby modes in memory2 Jul 2026US 2026/0188364 A1Everspin Technologies, Inc.
Most cited
By later US patents
- Synchronous interface for a nonvolatile memory331US 6,564,285 B1Intel Corporation · 2003
- Integrated circuit I/O using high performance bus interface325US 5,319,755 ARambus Inc. · 1994
- Bus system optimization316US 6,643,787 B1Rambus Inc. · 2003
- Memory circuitry having bus interface for receiving information in packets and access time registers282US 5,606,717 ARambus Inc. · 1997
- Memory module having memory devices containing internal device ID registers and method of initializing same261US 5,928,343 ARambus Inc. · 1999