Non-volatile memory device having high i/o efficiency based on separate command address protocol, operation method thereof, and storage device including same

A non-volatile memory device comprising:

• a plurality of memory blocks comprising memory cells;
• a page buffer circuit configured to store data sensed from the memory cells;
• a control logic circuit configured to direct writing of data to the memory cells or sensing of the data from the memory cells;
• a first channel, a second channel, and a third channel, each of the first channel, the second channel, and the third channel comprising at least one pad;
• and
• a transceiver configured to transmit the data to an external device or configured to receive the data,
• wherein the first channel is configured to receive a command and an address,
• wherein the second channel is configured to transmit and receive the data, and
• wherein the third channel is configured to receive a first control signal, and
• wherein the control logic circuit is configured to transmit a second control signal enabling the transceiver to a driving circuit in response to receiving a select chip enable packet through the first channel, and direct transmission or reception of the data through the second channel based on the select chip enable packet and the first control signal.

A method of operating a non-volatile memory device comprising a plurality of memory dies sharing a first channel, a second channel, and a third channel, the method comprising:

• receiving a first command to direct input of first data to a first memory die or output of the first data from the first memory die through the first channel;
• receiving a first select chip enable packet to select the first memory die through the first channel;
• controlling the first memory die to turn on at least one first driving circuit that drives a transceiver of the first memory die in response to receiving the first select chip enable packet;
• sensing, by the first memory die, a first transition of a first control signal received through the third channel;
• and
• controlling the transceiver of the first memory die to transmit or receive the first data through the second channel based on the first transition.