Synchronous interface for a nonvolatile memory

A method comprising:

• a.) specifying a beginning address of a plurality of addresses corresponding to a data burst by receiving a plurality of multiplexed addresses and control signals including a first strobe signal and a second strobe signal, latching a first portion of a selected multiplexed start address;
• and latching a second portion of the selected multiplexed start address, wherein the first and second portions form a demultiplexed address;
• b.) reading data from a flash memory in accordance with the addresses;
• c.) providing the data in synchronization with a clock signal;
• d.) generating a burst read address as the beginning address;
• and
• e.) repeating steps b) through d) in a burst read mode such that data stored at the plurality of addresses is provided sequentially, starting from the beginning address, during subsequent clock cycles.

An apparatus comprising:

• a plurality of flash memory banks, wherein consecutive addresses are interlace among the plurality of flash memory banks;
• interlace control logic generating bank latch enable signals in accordance with received multiplexed address signals, asynchronous control signals, and synchronous control signals including a clock signal;
• a plurality of bank latches to provide addresses to the plurality of banks in accordance with the bank latch enable signals;
• and
• a mode register, wherein the interlace control logic provides synchronous access to the plurality of memory banks in accordance with the multiplexed address signals and synchronous control signals to provide synchronous burst read data on consecutive cycles of the clock signal if the mode register is storing a first value.