Command address input buffer bias current reduction

A memory device comprising:

• a memory bank configured to store data;
• and
• command address circuitry configured to regulate access to the memory bank based on sets of command address signals, wherein the command address circuitry is configured to operate in a mode of a set of modes, the set of modes comprising a 1N mode and a 2N mode, wherein the memory device is configured to operate based on a clock signal comprising a plurality of clock cycles and a clock frequency, and wherein the clock frequency in the 2N mode is greater than or equal to the clock frequency in the 1N mode,
• for a two-cycle command comprising two sets of command address signals that are communicated using two clock cycles of the clock signal:
• in response to operating in the 1N mode, the command address circuitry is configured to:
• when triggered by a chip select signal, read a first set of command address signals of the two sets of command address signals, during a first 1N clock cycle of the clock signal;
• and
• read a second set of command address signals of the two sets of command address signals, immediately subsequent to the first set of command address signals, during a second 1N clock cycle of the clock signal immediately subsequent to the first 1N clock cycle, and
• in response to operating in the 2N mode, the command address circuitry is configured to:
• when triggered by the chip select signal, read the first set of command address signals during a first 2N clock cycle of the clock signal, wherein a second 2N clock cycle of the clock signal is immediately subsequent the first 2N clock cycle;
• and
• read the second set of command address signals during a third 2N clock cycle of the clock signal immediately subsequent to the second 2N clock cycle,
• wherein the command address circuitry comprises an input buffer configured to operate based on a biasing current supplied to the input buffer, and wherein the biasing current in the 2N mode of operation is different from the biasing current in the 1N mode of operation.

A memory device comprising:

• a memory bank configured to store data;
• and
• command address circuitry configured to regulate access to the memory bank based on command address signals, wherein the command address circuitry is configured to operate in a mode of a set of modes, the set of modes comprising a first mode and a second mode, wherein the memory device is configured to operate based on a clock signal comprising a plurality of clock cycles and a clock frequency, and wherein the clock frequency in the second mode of operation is greater than or equal to the clock frequency in the first mode of operation,
• for a two-cycle command comprising two sets of command address signals that are communicated using two clock cycles of the clock signal:
• in response to operating in the first mode, the command address circuitry is configured to:
• when triggered by a chip select signal, perform reads of consecutive sets of command address signals of the two sets of command address signals, on immediately consecutive clock cycles, and
• in response to operating in the second mode, the command address circuitry is configured to:
• when triggered by the chip select signal, perform reads and skip a clock cycle between reads of the consecutive sets of command address signals of the two sets of command address signals,
• wherein the command address circuitry comprises an input buffer configured to operate based on a biasing current supplied to the input buffer, and wherein the biasing current in the second mode of operation is different from the biasing current in the first mode of operation.

A method comprising:

• initializing a memory device in a mode of a set of operating modes, the memory device comprising command address circuitry configured to regulate access to a memory bank of the memory device based on command address signals, wherein the set of operating modes comprises a 2N mode and a 1N mode, wherein the memory device is configured to operate based on a clock signal comprising a plurality of clock cycles and a clock frequency, and wherein the clock frequency in the 2N mode of operation is greater than or equal to the clock frequency in the 1N mode of operation;
• for a two-cycle command comprising two sets of command address signals that are communicated using two clock cycles of the clock signal:
• reading, via the command address circuitry, a first set of command address signals of the two sets of command address signals, during a first clock cycle of the clock signal;
• and
• reading, via the command address circuitry, a second set of command address signals of the two sets of command address signals, immediately subsequent to the first set of command address signals, wherein reading the second set of command address signals comprises:
• in response to operating in the 1N mode, reading the second set of command address signals during a second clock cycle of the clock signal immediately subsequent to the first clock cycle;
• and
• in response to operating in the 2N mode, reading the second set of command address signals during a third clock cycle of the clock signal immediately subsequent to the second clock cycle, wherein a chip select signal is used for triggering reading the first set of command address signals in the 1N mode and the 2N mode,
• wherein the command address circuitry comprises an input buffer configured to operate based on a biasing current supplied to the input buffer, and wherein the biasing current in the 2N mode of operation is different from the biasing current in the 1N mode of operation.