Local internal discovery and configuration of individually selected and jointly selected devices

A method for operating a memory controller configured to control a first memory device having an array of memory cells, the method comprising:

• transmitting a connectivity read command to the first memory device over a command/address link to cause the first memory device to output a sequence of bit patterns on memory-side data lines;
• receiving at a data interface comprising a set of controller-side data pins of which at least a subset are communicatively coupled to at least a subset of the memory-side data lines, a sequence of bit patterns in response to the connectivity read command;
• detecting a connectivity state between the memory controller and the first memory device based on the sequence of bit patterns received on the set of controller-side data pins of the data interface, wherein the connectivity state indicates a detected mapping between at least one of the controller-side data pins of the data interface and at least one data line of the memory-side data lines of the memory device-that was used in communicating the sequence of bit patterns;
• and
• configuring the memory controller for communicating with the first memory device based on the connectivity state.

A memory controller for controlling a memory device having an array of memory cells for storing data, the memory controller comprising:

• a command/address interface to transmit a predetermined bit sequence to the memory device over a command/address link;
• a data interface to receive a plurality of bit patterns from the memory device, each bit pattern received corresponding to a subset of bit values from the predetermined bit sequence, each bit pattern having a single bit representing a first binary logic state and remaining bits other than the single bit in the bit pattern representing a second binary logic state that is different from the first binary logic state;
• and
• a circuit to detect a connectivity configuration of each pin of a data interface of the memory device based on the plurality of bit patterns received by the data interface of the memory controller, wherein a set of bits received by an individual data pin of the data interface over the plurality of bit patterns indicates a connectivity configuration of the individual data pin.