Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption

A method of operating a memory controller, the method comprising:

• instructing a memory device to perform a write operation having a first operation mode and a second operation mode;
• generating a clock signal relating to the first operation mode and the second operation mode for the write operation of the memory device;
• switching a frequency of the clock signal to a first frequency during the first operation mode of the write operation according to de-assertion of a status signal of the memory device provided to the memory controller from the memory device;
• and
• switching the frequency of the clock signal to a second frequency during the second operation mode of the write operation according to assertion of the status signal of the memory device provided to the memory controller from the memory device,
• wherein the first operation mode of the write operation includes that the memory controller transmits write data to the memory device, and the second operation mode of the write operation includes that the memory device programs the write data to memory cells of the memory device, and
• wherein the first frequency of the clock signal is a high frequency and the second frequency of the clock signal is lower than the first frequency of the clock signal.

A method of operating a memory device, the method comprising:

• performing a read operation in response to a read command received from a memory controller, the read operation having a first operation mode and a second operation mode;
• receiving a status check signal for checking an operation status of the memory device from the memory controller;
• transmitting a status signal indicating an operation status of the read operation to the memory controller;
• and
• transmitting a clock signal that is toggled at a changed frequency relating to the status signal,
• wherein the clock signal is switched to a low frequency during the first operation mode of the read operation according to assertion of the status signal, and the clock signal is switched to a high frequency during the second operation mode of the read operation according to de-assertion of the status signal, and
• wherein the first operation mode of the read operation includes that the memory device reads data stored in memory cells of the memory device, and the second operation mode of the read operation includes that the memory device transmits the data read from the memory cells to the memory controller.