Multi-channel memory
AssigneeSK hynix Inc.
InventorsHong Ki MOON, Min Su PARK
Life of this patent
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Abstract
A memory includes a first command address decoder configured to decode a first chip selection signal and first command address signals and generate first control signals, a second command address decoder configured to decode a second chip selection signal and second command address signals and generate second control signals during a multi-channel mode and configured to decode the second chip selection signal and the first command address signals and generate second control signals during a multi-rank mode, a first memory core including first memory cells and being controlled by the first control signals, and a second memory core including second memory cells and being controlled by the second control signals.
Claims19
A memory comprising:
- a first command address decoder configured to decode a first chip selection signal and first command address signals, and generate first control signals;
- a second command address decoder configured to decode a second chip selection signal and second command address signals, and generate second control signals during a multi-channel mode, and configured to decode the second chip selection signal and the first command address signals, and generate second control signals during a multi-rank mode;
- a first memory core including first memory cells, the first memory core being controlled by the first control signals;
- and
- a second memory core including second memory cells, the second memory core being controlled by the second control signals.
A memory comprising:
- a first command address decoder configured to decode a first chip selection signal and first command address signals, and generate first control signals;
- a second command address decoder configured to decode a second chip selection signal and second command address signals, and generate second control signals during a multi-channel mode;
- a first memory core including first memory cells, the first memory core being controlled by the first control signals;
- and
- a second memory core including second memory cells, the second memory core controlled by the second control signals during the multi-channel mode, and the second memory core controlled by the first control signals during a single-rank mode.
A memory comprising:
- a first command address decoder configured to decode command address signals and a chip selection signal;
- a second command address decoder configured to decode at least some different signals from the first command address decoder;
- a first data transmission and reception (transmission/reception) circuit configured to transmit and receive data through first data terminals;
- a second data transmission/reception circuit configured to transmit and receive data through second data terminals;
- and
- a configuration mode setting circuit configured to control activation and deactivation of the second command address decoder and the second data transmission/reception circuit depending on an operation mode.
Dependencies are inferred from the claim text.