Memory module having memory devices containing internal device ID registers and method of initializing same

An apparatus for assigning identification values to memories, the apparatus comprising:

• (1) a daisy-chained line coupled to a master, a first memory and a second memory;
• (2) a data bus coupled to the master, the first memory, and the second memory;
• (3) reset circuitry for sending a reset signal from the master to the first and second memories via the daisy-chained line and for resetting identifiers of the first and second memories in response to the reset signal;
• (4) circuitry within the master for generating first and second identification values and sending them to the first and second memories via the daisy-chained line;
• (5) circuitry within the first memory for storing at a first predetermined time the first identification value on the daisy-chained line as an identifier for the first memory;
• and
• (6) circuitry within the second memory for storing at a second predetermined time the second identification value on the daisy-chained line as an identifier for the second memory.

A memory module having a plurality of memory devices, the memory module comprises:

• a bus having a plurality of signal lines including a reset signal line which is electrically connected to the plurality of memory devices;
• a first memory device including:
• at least one memory section having a plurality of memory cells which are accessed using address signals;
• an internal register to store an identification value to identify the first memory device on the bus;
• and
• interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the first memory device stores the identification value which identifies the first memory device on the bus;
• and
• a second memory device including:
• at least one memory section having a plurality of memory cells which are accessed using address signals;
• an internal register to store an identification value to identify the second memory device on the bus;
• and
• interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the second memory device stores the identification value which identifies the second memory device on the bus.

A method of assigning identification values to a plurality of memory devices disposed on a memory module, the plurality of memory devices include a first memory device having a programmable register for storing an identification value and second memory device having a programmable register for storing an identification value, wherein the memory module includes a bus to electrically connect the first and the second memory devices, wherein the bus includes a plurality of signal lines including a reset signal line which electrically connects the first and the second memory devices, a clock signal line for receiving an external clock signal, and data lines for receiving first and second identification values, the method comprising:

• applying the first identification value on the data lines for a predetermined number of clock cycles of the external clock signal;
• applying a reset signal to the first memory device wherein, in response to the reset signal received by the first memory device, the programmable register in the first memory device stores the first identification value;
• applying the second information value on the data lines for the predetermined number of clock cycles of the external clock signal;
• and
• applying a reset signal to the second memory device wherein, in response to the reset signal received by the second memory device, the programmable register in the second memory device stores the second identification value.

A method of assigning identification values to first and second memory devices disposed on a memory module having a bus which electrically connects the first and the second memory devices, wherein the bus includes a plurality of signal lines including a daisy-chained signal line which electrically connects the first and the second memory devices in a daisy-chained manner, the method comprising:

• applying first and second identification values on the daisy-chained signal line;
• storing the first identification value in a programmable register in the first memory device at a first predetermined time;
• and
• storing the second identification value in a programmable register in the second memory device at a second predetermined time.