G11C 5/066
Means for reducing external access-lines for a semiconductor memory clip
Official title: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
G11C5/066 (Means for reducing external access-lines for a semiconductor memory clip) appears on 670 US grants and 526 published applications in this corpus.
Search patents in G11C- Granted patents
- 670
- Published applications
- 526
- Assignees
- 168
- Inventors
- 814
- Latest grant
- 4 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 2 | 0 |
| 1980 | 1 | 0 |
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 2 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 4 | 0 |
| 1988 | 5 | 0 |
| 1989 | 1 | 0 |
| 1990 | 10 | 0 |
| 1991 | 9 | 0 |
| 1992 | 5 | 0 |
| 1993 | 9 | 0 |
| 1994 | 5 | 0 |
| 1995 | 10 | 0 |
| 1996 | 12 | 0 |
| 1997 | 13 | 0 |
| 1998 | 22 | 0 |
| 1999 | 18 | 0 |
| 2000 | 30 | 0 |
| 2001 | 20 | 6 |
| 2002 | 16 | 23 |
| 2003 | 13 | 3 |
| 2004 | 13 | 9 |
| 2005 | 8 | 21 |
| 2006 | 9 | 26 |
| 2007 | 14 | 19 |
| 2008 | 21 | 14 |
| 2009 | 14 | 22 |
| 2010 | 20 | 17 |
| 2011 | 16 | 12 |
| 2012 | 10 | 9 |
| 2013 | 13 | 17 |
| 2014 | 20 | 21 |
| 2015 | 15 | 13 |
| 2016 | 20 | 13 |
| 2017 | 23 | 31 |
| 2018 | 18 | 19 |
| 2019 | 34 | 40 |
| 2020 | 29 | 41 |
| 2021 | 32 | 28 |
| 2022 | 26 | 28 |
| 2023 | 32 | 27 |
| 2024 | 26 | 24 |
| 2025 | 26 | 28 |
| 2026 | 16 | 15 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Ground pin package substrate, semiconductor device, and electronic device4 Aug 2026US 12,702,029 B2Huawei Technologies Co., Ltd.
- Semiconductor device and stack type semiconductor memory device including the same28 Jul 2026US 12,694,909 B2SK hynix Inc.
- Memory device and operation method for data movement within memory sections and through external interfaces of memory device28 Jul 2026US 12,694,910 B2Piecemakers Technology, Inc.
- Reduced pin count stackable memory16 Jun 2026US 12,657,121 B1Raytheon Company
- Methods and apparatus for eviction in dual datapath victim cache system16 Jun 2026US 12,657,134 B2Texas Instruments Incorporated
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Methods and apparatus to facilitate read-modify-write support in a victim cache17 Sep 2026US 2026/0277825 A1
- Semiconductor apparatus and semiconductor system having independent data input/output period, and operating method of the semiconductor system27 Aug 2026US 2026/0253625 A1SK hynix Inc.
- Multiplexing distinct signals on a single pin of a memory device16 Jul 2026US 2026/0205332 A1Lodestar Licensing Group LLC
- Scan-path integrated circuit memory with output bus feedback9 Jul 2026US 2026/0196286 A1SambaNova Systems, Inc.
Most cited
By later US patents
- Solid state memory system including plural memory chips and a serialized bus546US 5,430,859 ASunDisk Corporation · 1995
- Apparatus for synchronously generating clock signals in a data processing system430US 5,243,703 ARambus Inc. · 1993
- Integrated circuit I/O using high performance bus interface325US 5,319,755 ARambus Inc. · 1994
- Memory circuitry having bus interface for receiving information in packets and access time registers282US 5,606,717 ARambus Inc. · 1997
- Memory module having memory devices containing internal device ID registers and method of initializing same261US 5,928,343 ARambus Inc. · 1999