Reduced pin count stackable memory

A stackable memory system comprising:

• a controller including:
• an address decoder, and a set of controller output pins;
• and a stackable memory device including:
• a first surface with a set of input pins, the set of input pins coupled to the set of controller output pins, the set of input pins configured to receive chip select signals from the address decoder;
• a second surface with a set of output pins, the set of output pins arranged in a matching configuration to the set of input pins to enable coupling and stacking of multiple stackable memory devices;
• and a cascade routing signal scheme including:
• a set of dedicated point-to-point signal paths configured to shift the chip select signals from the set of input pins by one bit when propagated to the set of output pins;
• and an enable point-to-point signal path configured to connect an input pin to an enable component of the stackable memory device.

A method of accessing computer memory from a stackable memory system, the method comprising:

• determining a device address for a target stackable memory device in a stackable memory device system;
• determining a dedicated output pin of a controller corresponding to the target stackable memory device;
• generating, corresponding to the device address, a chip select signal in the controller;
• transmitting, through the dedicated output pin, the chip select signal through a cascade routing scheme of a first stackable memory device, the cascade routing scheme configured to shift the chip select signal from a set of input pins by one bit when propagated to a set of output pins;
• and
• activating, upon receipt of the chip select signal after passing through the first stackable memory device, an enable component of the target stackable memory device.