Solid state memory system including plural memory chips and a serialized bus

A mass storage system for use with a computer system, comprising:

• a plurality of solid-state memory chips, each having a large number of memory cells therein;
• a memory chip controller coupled to the computer system for controlling said plurality of memory chips;
• a device bus for connecting said memory chip controller to each of said plurality of solid-state memory chips, said device bus carrying serialized address, data and command information, thereby substantially reducing the number of connections between said memory chip controller and each of said plurality of memory chips;
• one or more memory submodules each containing a plurality of memory-device mounts, each of said plurality of memory-device mounts for receiving one of said plurality of memory chips;
• one or more backplanes each containing a plurality of submodule mounts for receiving one of said one or more memory submodules;
• said device bus being coupled to each memory submodule for connection to each memory-device mount and therefore to each memory chip thereon;
• a set of device-select pinouts on each of said memory chips;
• a set of pads on each of said memory-device mounts for connection to the set of device-select pinouts of a memory chip mounted thereon, each set of pads being partitioned into a first and second subset of pads;
• each first subset of pads providing a first group of grounded pads configurations to define unique addresses for all memory-device mounts and therefore addresses for corresponding memory chips mounted on each memory submodule;
• and
• each second subset of pads being connected to pads on a corresponding submodule mount and providing a second group of grounded pads configurations to define unique addresses for all submodule mounts and therefore addresses for corresponding memory submodules mounted on said one or more backplanes.

A mass storage system for use with a computer systems comprising:

• a plurality of solid-state memory chips, each having a large number of memory cells therein;
• a memory chip controller coupled to the computer system for controlling said plurality of memory chips;
• a device bus for connecting said memory chip controller to each of said plurality of solid-state memory chips, said device bus carrying serialized address, data and command information, thereby substantially reducing the number of connections between said memory chip controller and each of said plurality of memory chips;
• each solid-state memory device chip further including:
• a serial protocol logic for controlling a protocol of the serialized address, data and command information carried on the device bus, said serial protocol logic comprising;
• first routing and converting means for routing and converting serialized addresses from the device bus to a parallel address bus;
• second routing and converting means for routing and converting serialized data from the device bus to a parallel data bus;
• third routing and converting means for routing and converting serialized command codes from the device bus to a plurality of parallel command lines;
• a pointer shift register means for capturing a code from the device bus;
• a pointer decode means for selectively enabling one of the first, second and third routing and converting means;
• and
• a serial protocol control signal from the device bus for enabling said pointer shift register means for capturing the code from the device bus while disabling said first, second and third routing and converting means, and for disabling said pointer shift register means after the code has been captured and enabling a selected one of said first, second and third routing and converting means.