Scan-path integrated circuit memory with output bus feedback

An integrated circuit comprising:

• a memory array comprising a plurality of rows of storage elements;
• an N-bit wide input buffer coupled to the memory array and enabled to load N bits of data in parallel during a first phase of a clock signal;
• an output multiplexer coupled to the memory array and configured to output N bits of data in parallel from a selected row of the plurality of rows on an N-bit wide data output bus;
• an input multiplexer coupled to the input buffer and configured to select, as input to the input buffer, between a functional data path and a scan input set, the scan input set comprising a scan-in line coupled to a most-significant input of the input buffer and a set of feedback lines each coupling an output line of the data output bus to a next-lower-significance input of the input buffer;
• and
• a scan-out connection coupling a least-significant output line of the data output bus to a scan-out line of a scan chain;
• wherein, during a scan operation indicated by a scan enable signal, the input multiplexer selects the scan input set, storage elements of the selected row are enabled to load data from the input buffer in parallel during a second phase of the clock signal, and the scan-in line, the input buffer, the selected row of storage elements, and the scan-out connection form a serial scan path through the memory array.

An integrated circuit comprising:

• a memory array comprising M rows of N storage elements each, having an N-bit wide parallel input, an N-bit wide parallel output, a scan input, and a scan output, wherein N and M are positive integers greater than one;
• a memory built-in self-test circuit coupled to the memory array;
• functional circuitry coupled to the memory array;
• an N-bit wide input buffer coupled to the memory array and enabled to load data during a first phase of a clock signal, the storage elements of a selected one of the M rows enabled to load data from the input buffer in parallel during a second phase of the clock signal;
• an input multiplexer coupled to the input buffer and configured to select as input to the input buffer between:
• a first input coupled to the functional circuitry, a second input coupled to the memory built-in self-test circuit, and a third input comprising the scan input coupled to a most-significant input of the input buffer and feedback lines from upper output lines of the N-bit wide parallel output coupled to remaining inputs of the input buffer;
• and
• control circuitry configured to:
• in a serial scan mode, select the third input and fix or increment the selected row to shift data serially through the memory array via the scan input and the scan output;
• in a memory built-in self-test mode, select the second input and use test addresses from the memory built-in self-test circuit for parallel access to the memory array;
• and in a normal operation mode, select the first input and use the functional circuitry for parallel access to the memory array;
• wherein the scan output is coupled to a least-significant line of the N-bit wide parallel output.