Ground pin package substrate, semiconductor device, and electronic device

An electronic device comprising:

• a circuit board;
• and
• a semiconductor device disposed on the circuit board and comprising:
• a package substrate comprising:
• a substrate body;
• and
• a plurality of unit regions arranged on the substrate body, wherein each of the unit regions comprises two first pin structures, wherein each of the two first pin structures comprises six first pins, wherein the six first pins are disposed, with two of the six first pins in a row, to form three parallel rows of two pins, and wherein the three parallel rows of two pins comprises:
• a first row of single-ended signal pins;
• a second row of differential signal pins;
• and
• a third row of single-ended signal pins,
• wherein the two pins in the first row of pins and the two pins in the second row of pins are located at four vertices of a first parallelogram,
• wherein the two pins in the second row of pins and the two pins in the third row of pins are located at four vertices of a second parallelogram,
• wherein the first parallelogram and the second parallelogram are arranged axisymmetric about the second row of pins,
• wherein in each of the unit regions, the two first pin structures are arranged in a row direction of the second row of pins, and wherein the two first pin structures are axisymmetric,
• wherein in each of the unit regions, a first distance between first rows of pins in the two first pin structures is greater than a second distance between second rows of pins in the two first pin structures, and
• wherein the single-ended signal pins and the differential signal pins are disposed on the circuit board and are electrically coupled to the semiconductor device;
• and
• a chip disposed on the package substrate and operably coupled with the six first pins.

A package substrate comprising:

• a substrate body;
• and
• a plurality of unit regions arranged on the substrate body, wherein each of the unit regions comprises two first pin structures, wherein each of the two first pin structures comprises six first pins, wherein the six first pins are disposed in three parallel rows of two pins, and wherein the three parallel rows of two pins comprises:
• a first row of single-ended signal pins;
• a second row of differential signal pins;
• and
• a third row of single-ended signal pins,
• wherein the two pins in the first row of pins and the two pins in the second row of pins are located at four vertices of a first parallelogram,
• wherein the two pins in the second row of pins and the two pins in the third row of pins are located at four vertices of a second parallelogram,
• wherein the first parallelogram and the second parallelogram are arranged axisymmetric about the second row of pins,
• wherein in each of the unit regions, the two first pin structures are arranged in a row direction of the second row of pins, and wherein the two first pin structures are axisymmetric, and
• wherein in each of the unit regions, a first distance between first rows of pins in the two first pin structures is greater than a second distance between second rows of pins in the two first pin structures.