Memory device and operation method for data movement within memory sections and through external interfaces of memory device

A memory device, comprising:

• a memory array, divided into a plurality of memory sections, each memory section comprising a plurality of memory cells;
• a plurality of data transfer circuits, each data transfer circuit being disposed between two memory sections;
• wherein a data movement occurring from all or a selected set of bit-lines or bit-line pairs between any two adjacent memory sections of the memory array is performed, data signals of all or the selected set of bit-lines or bit-line pairs of two adjacent memory sections are sensed, latched, buffered and repeated during the data movement by a data transfer circuit disposed between two adjacent memory sections, and the data movement is sequentially performed between two memory sections to facilitate the transfer of data signals to any memory section of the memory array without the need for global or trans-multiple-section data lines, wherein each data transfer circuit comprises a plurality of third-type data transfer circuits, and each third-type data transfer circuit comprises:
• a first first-type sensing buffer circuit, comprising a plurality of first BLSAs, and each first BLSA being coupled to a bit-line or bit-line pair of a memory section;
• a first multiplexer, coupled to the plurality of first BLSAs, and configured to select a set of first BLSAs from the plurality of first BLSAs;
• a second multiplexer, coupled to the first multiplexer;
• and
• a second first-type sensing buffer circuit, comprising a plurality of second BLSAs, and each second BLSA being coupled to the second multiplexer and a bit-line or bit-line pair of an adjacent memory section;
• wherein the first multiplexer is configured to connect the selected set of first BLSAs to the second multiplexer, the second multiplexer is configured to select a set of second BLSAs from the plurality of second BLSAs and connect the selected set of second BLSAs to the first multiplexer;
• wherein the data signals on bit-lines or bit-line pairs coupled to the selected set of first BLSAs in the memory section are sensed, latched and buffered by the selected set of first BLSAs, the latched data signals are driven and transferred to the selected set of second BLSAs by the selected set of first BLSAs through connection operations of the first multiplexer and the second multiplexer, the data signals are transferred to bit-lines or bit-line pairs coupled to the selected set of second BLSAs in the adjacent memory section by the selected set of second BLSAs, and the data signals are sequentially transferred across subsequent memory sections through other data transfer circuits which are coupled to two adjacent memory sections.