G11C 29/50016
Of retention
Official title: {of retention}
G11C29/50016 (Of retention) appears on 552 US grants and 482 published applications in this corpus.
Search patents in G11C- Granted patents
- 552
- Published applications
- 482
- Assignees
- 152
- Inventors
- 965
- Latest grant
- 5 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 2 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 4 | 0 |
| 1990 | 2 | 0 |
| 1991 | 2 | 0 |
| 1992 | 3 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 8 | 0 |
| 1996 | 5 | 0 |
| 1997 | 7 | 0 |
| 1998 | 5 | 0 |
| 1999 | 19 | 0 |
| 2000 | 8 | 0 |
| 2001 | 7 | 1 |
| 2002 | 5 | 9 |
| 2003 | 13 | 14 |
| 2004 | 11 | 17 |
| 2005 | 16 | 23 |
| 2006 | 21 | 18 |
| 2007 | 15 | 20 |
| 2008 | 14 | 11 |
| 2009 | 11 | 14 |
| 2010 | 15 | 19 |
| 2011 | 13 | 12 |
| 2012 | 12 | 14 |
| 2013 | 20 | 17 |
| 2014 | 24 | 40 |
| 2015 | 47 | 28 |
| 2016 | 29 | 37 |
| 2017 | 28 | 34 |
| 2018 | 34 | 31 |
| 2019 | 30 | 17 |
| 2020 | 21 | 15 |
| 2021 | 20 | 20 |
| 2022 | 12 | 16 |
| 2023 | 19 | 27 |
| 2024 | 23 | 14 |
| 2025 | 13 | 9 |
| 2026 | 4 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Controlling erase-to-program delay for improving data retention5 May 2026US 12,620,445 B2Micron Technology, Inc.
- Adaptable charge loss scanning cadence in a memory sub-system17 Mar 2026US 12,580,037 B1Micron Technology, Inc.
- Management of refresh operations in an embedded dynamic random access memories (DRAMs) having canary cells20 Jan 2026US 12,531,103 B2NXP USA, Inc.
- Adaptive scanning of memory devices with supervised learning6 Jan 2026US 12,517,659 B2Micron Technology, Inc.
- Flash memory for performing margin read test operation and margin read test system including the same9 Dec 2025US 12,494,263 B2Samsung Electronics Co., Ltd.
- Method, system, device, and storage medium for determining wck-on value of lpddr chip30 Jul 2026US 2026/0221212 A1Shenzhen Rayson Technology Co., Ltd.
- Defect detection method for memory device2 Jul 2026US 2026/0188406 A1Powerchip Semiconductor Manufacturing Corporation
- Dram retention test method for dynamic error correction2 Jul 2026US 2026/0188410 A1Rambus Inc.
- Testing method for memory device18 Jun 2026US 2026/0171179 A1Powerchip Semiconductor Manufacturing Corporation
- Adaptable charge loss scanning cadence in a memory sub-system5 Mar 2026US 2026/0066031 A1Micron Technology, Inc.
Most cited
By later US patents
- Scannable sense amplifier circuit421US 5,915,084 AAdvanced Micro Devices, Inc. · 1999
- Selective application of voltages for testing storage cells in semiconductor memory arrangements248US 5,157,629 AHitachi, Ltd. · 1992
- Memory device testing to support address-differentiated refresh rates115US 7,444,577 B2Rambus Inc. · 2008
- Method for apparatus for tracking errors in a memory system111US 6,560,725 B1Madrone Solutions, Inc. · 2003
- Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for lengthening a refresh interval101US 6,449,204 B1Mitsubishi Denki Kabushiki Kaisha · 2002