Management of refresh operations in an embedded dynamic random access memories (DRAMs) having canary cells

A dynamic random access memory (DRAM), comprising:

• a plurality of main bit cells, each with a capacitive storage element;
• a first set of write bit lines and a first set of write word lines, wherein each main bit cell is coupled to a corresponding write bit line of the first set of write bit lines and a corresponding write word line of the first set of write word lines;
• a plurality of canary cells, each having a capacitive storage element;
• a second set of write bit lines and a second set of write word lines, wherein each canary cell is coupled to a corresponding write bit line of the second set of write bit lines and a corresponding write word line of the second set of write word lines;
• a voltage generator configured to provide a selected one of multiple write bit line voltages to each write bit line of the second set of write bit lines, wherein the selected one of the multiple write bit line voltages provides a higher write bit line voltage to each write bit line of the second set of write bit lines as compared to a write bit line voltage provided to each write bit line of the first set of write bit lines during a write operation such that canary cells coupled to receive the higher write bit line voltage are more susceptible to leakage as compared to any of the main bit cells of the plurality of main bit cells;
• a refresh circuit configured to perform refreshes of the plurality of main bit cells and the plurality of canary cells in accordance with a refresh rate;
• and
• a control circuit configured to write a same logic state into each canary cell of the plurality of canary cells and configured to poll at least a portion of the plurality of canary cells to determine whether or not sensed logic states are the same logic state.