Adaptable charge loss scanning cadence in a memory sub-system
AssigneeMicron Technology, Inc.
InventorSteven Michael Kientz
Life of this patent
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AssigneeMicron Technology, Inc.
InventorSteven Michael Kientz
Estimating the term…
A system includes a memory device and a processing device operatively coupled with the memory device to perform operations including determining to perform a first scan operation on a first block of a plurality of blocks of the memory device; responsive to determining to perform the first scan operation, adding an indication of the first scan operation to a queue of pending scan operations corresponding to scanning the plurality of blocks; determining whether a number of pending scan operations of the queue of pending scan operations satisfies a threshold condition; and responsive to determining that the number of pending scan operations does not satisfy the threshold condition, causing a first subset of scan operations of the queue of pending scan operations to be performed on respective blocks of the plurality of blocks.
A memory sub-system comprising:
A method comprising:
A computer-readable non-transitory storage medium comprising instructions, that when read, cause one or more processing devices to perform operations comprising:
Dependencies are inferred from the claim text.