Testing method for memory device
AssigneePowerchip Semiconductor Manufacturing Corporation
InventorsTsai-Ko Teng, Chia-Yen Wu
Life of this patent
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Abstract
A testing method for a memory device is provided. The memory device includes a memory array and a decoder circuit. The decoder circuit operates based on a first reference voltage. The memory array operates based on a second reference voltage. The testing method includes: dividing the memory array into memory blocks; adjusting a voltage value of at least one of the first reference voltage and the second reference voltage to sequentially access the memory blocks and receiving failed bit counts (FBCs) of the memory blocks after accessing operations; and counting a plurality of memory block numbers corresponding to different voltage values of the first reference voltage and/or the second reference voltage and the FBCs.
Claims15
A testing method for a memory device, comprising a memory array and a decoder circuit, wherein the decoder circuit operates based on a first reference voltage, wherein the memory array operates based on a second reference voltage, the testing method comprising:
- dividing the memory array into a plurality of memory blocks;
- adjusting a voltage value of at least one of the first reference voltage and the second reference voltage to sequentially perform an accessing operation on the memory blocks and receiving a plurality of failed bit counts of the memory blocks after the accessing operation;
- and
- counting a plurality of memory block numbers corresponding to a plurality of different voltage values of at least one of the first reference voltage and the second reference voltage and the failed bit counts.
Dependencies are inferred from the claim text.