Selective application of voltages for testing storage cells in semiconductor memory arrangements

A semiconductor memory comprising:

• a memory cell including a data storage capacitor, having a pair of electrodes, and a MISFET coupled in series with said capacitor;
• and
• a voltage generating circuit, powered by a power source voltage, for providing a voltage of about a half of said power source voltage to one of said pair of electrodes, the other of said pair of electrodes being coupled to said MISFET;
• wherein said voltage generating circuit comprises a voltage dividing circuit which has a first resistor means having one end coupled to said power source voltage, a second resistor means having one end coupled to a predetermined voltage, a first node, a first MISFET of a first channel conductivity type, configured to operate as a diode, coupled between a second end of said first resistor means and said first node, and a second MISFET of a second channel conductivity type, configured to operate as a diode, coupled between a second end of said second resistor means and said first node, a first output MISFET of said first channel conductivity type having a gate coupled to the common connection of said first MISFET and said first resistor means, and a second output MISFET of said second channel conductivity type having a gate coupled to the common connection of said second MISFET and said second resistor means and having its source connected to the source of said first output MISFET, and wherein said first and second MISFETs have threshold voltage levels of absolute value smaller than that of the corresponding first and second output MISFETs, respectively, and wherein an output voltage of about a half of said power source voltage is obtained from said common source connection of said first and second output MISFETs.