Controlling erase-to-program delay for improving data retention
AssigneeMicron Technology, Inc.
InventorZhongyuan Lu
Life of this patent
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Abstract
A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including identifying an erased block of the memory array, causing a set of cells addressable by a target wordline of the erased block to be set to a target threshold voltage, determining an amount of threshold voltage shift with respect to the target threshold voltage after a delay, determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric, and in response to determining that the amount of threshold voltage shift is sufficient, releasing the erased block for programming.
Claims20
A memory device comprising:
- a memory array;
- and
- control logic, operatively coupled to the memory array, to perform operations comprising:
- identifying an erased block of the memory array;
- causing, at a first time, a set of cells addressable by a target wordline of the erased block to be programmed to a target threshold voltage different from an erase state;
- determining an amount of threshold voltage shift with respect to the target threshold voltage at a second time after the first time, wherein a difference between the second time and the first time is defined by a delay;
- determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric;
- and
- in response to determining that the amount of threshold voltage shift is sufficient, releasing the erased block for programming.
A method comprising:
- identifying, by a processing device, an erased block of a memory device;
- causing, by the processing device at a first time, a set of cells addressable by a target wordline of the erased block to be programmed to a target threshold voltage different from an erase state;
- determining, by the processing device, an amount of threshold voltage shift with respect to the target threshold voltage at a second time after the first time, wherein a difference between the second time and the first time is defined by a delay;
- determining, by the processing device, whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric;
- and
- in response to determining that the amount of threshold voltage shift is sufficient, releasing, by the processing device, the erased block for programming.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- identifying an erased block of a memory array;
- causing, at a first time, a set of cells addressable by a target wordline of the erased block to be programmed to a target threshold voltage different from an erase state;
- determining an amount of threshold voltage shift with respect to the target threshold voltage at a second time after the first time, wherein a difference between the second time and the first time is defined by a delay;
- determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric;
- and
- in response to determining that the amount of threshold voltage shift does not satisfy the threshold condition, re-determining the amount of threshold voltage shift after the delay.
Dependencies are inferred from the claim text.