G11C 16/3422
Circuits or methods to evaluate read or write disturbance in nonvolatile memory
Official title: {Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem}
G11C16/3422 (Circuits or methods to evaluate read or write disturbance in nonvolatile memory) appears on 246 US grants and 245 published applications in this corpus.
Search patents in G11C- Granted patents
- 246
- Published applications
- 245
- Assignees
- 66
- Inventors
- 437
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 2 | 0 |
| 2000 | 1 | 0 |
| 2001 | 0 | 0 |
| 2002 | 1 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 1 |
| 2006 | 1 | 5 |
| 2007 | 8 | 10 |
| 2008 | 5 | 7 |
| 2009 | 4 | 4 |
| 2010 | 5 | 4 |
| 2011 | 5 | 7 |
| 2012 | 6 | 9 |
| 2013 | 10 | 13 |
| 2014 | 14 | 23 |
| 2015 | 24 | 17 |
| 2016 | 21 | 24 |
| 2017 | 18 | 9 |
| 2018 | 11 | 11 |
| 2019 | 15 | 18 |
| 2020 | 19 | 13 |
| 2021 | 17 | 11 |
| 2022 | 13 | 15 |
| 2023 | 12 | 17 |
| 2024 | 20 | 12 |
| 2025 | 8 | 6 |
| 2026 | 4 | 9 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Cascade model for determining read level voltage offsets based on wordline group memory cells29 Sep 2026US 12,749,541 B2Micron Technology, Inc.
- Apparatus and methods for in-place read refresh for nonvolatile memory devices18 Aug 2026US 12,712,032 B2SanDisk Technologies LLC
- Memory system, control method thereof, and program7 Apr 2026US 12,597,475 B2Kioxia Corporation
- Memory device for performing read operation20 Jan 2026US 12,531,126 B2SK hynix Inc.
- Apparatus and methods for read retry with conditional data refresh25 Nov 2025US 12,482,527 B2SanDisk Technologies LLC
- Memory system, control method thereof, and program30 Jul 2026US 2026/0221202 A1Kioxia Corporation
- Storage device that analyzes deterioration characteristics of memory blocks and performs deterioration block management operation9 Jul 2026US 2026/0196281 A1Samsung Electronics Co., Ltd.
- Read disturb tracking for decks of a memory block21 May 2026US 2026/0141964 A1Micron Technology, Inc.
- Method and system for enhancing lifespan of a nand flash memory23 Apr 2026US 2026/0112426 A1Samsung Electronics Co., Ltd.
- Adaptive integrity scan in a memory sub-system9 Apr 2026US 2026/0100234 A1Micron Technology, Inc.
Most cited
By later US patents
- Compensating for coupling during read operations of non-volatile memory657US 7,196,928 B2SanDisk Corporation · 2007
- Read operation for non-volatile storage that includes compensation for coupling510US 7,187,585 B2SanDisk Corporation · 2007
- Method for operating non-volatile memory device and memory controller354US 9,117,536 B2Samsung Electronics Co., Ltd. · 2015
- Background selection of voltage reference values for performing memory read operations207US 8,638,602 B1Western Digital Technologies, Inc. · 2014
- Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks184US 5,715,193 AMicron Quantum Devices, Inc. · 1998