Apparatus and methods for in-place read refresh for nonvolatile memory devices

A method of operating a memory device, comprising steps of:

• providing a memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state;
• determining that the memory cells have experienced significant read disturb;
• without erasing the memory cells, programming the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state;
• and
• wherein the step of determining that the memory cells have experienced significant read disturb occurs in response to a determination that a count of memory cells in a voltage range that is below a voltage range associated with the programmed data state is greater than a predetermined threshold.

A memory device, comprising:

• a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state;
• and circuitry configured to:
• determine that the memory cells have experienced significant read disturb;
• without erasing the memory cells, program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state, and
• set a reference voltage SLCR for use during read operations from a first level to a higher second level after programming the memory cells in the programmed data state directly to the higher threshold voltages.

A computing system, comprising:

• a processor unit;
• a plurality of flash memory packages in electrical communication with the processor unit;
• at least one of the flash memory packages including a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state;
• and
• the at least one of the flash memory packages further including circuitry that is configured to:
• determine that the memory cells have experienced significant read disturb,
• without erasing the memory cells, program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state, and
• set a reference voltage SLCR for use during read operations from a first level to a higher second level after programming the memory cells in the programmed data state directly to the higher threshold voltages.