US 5,715,193 A · Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks

Abstract

A memory circuit including at least one of flash memory calls organized into one or more physically separate decode blocks and a controller which monitors the disturb effect on each independently erasable "erase" block of cells of each decode block due to erasures of other erase blocks in the same decode block, and a method of operating such a circuit. Preferably, the controller controls memory operations of each array in addition to monitoring the disturb effect on each erase block. The disturb effect causes cells of an erase block to lose charge from their floating gates each time an erase operation is performed on another erase block in the same decode block. Preferably, each time an erase block is erased, the controller updates a table for the decode block which contains the erased block by adding a unit of disturb to the count for each other erase block in the decode block and resetting the count for the erased block to zero. Also preferably, the controller performs a refresh operation on each erase block whose disturb count reaches a predetermined maximum value. During the refresh operation, any necessary recovery procedures are performed to restore the proper charge to the floating gate of each cell of the erase block, thus preventing any erroneous reads of data that would otherwise occur (due to the disturb effect) absent performance of the refresh operation.

Claims34

Dependent claims

A flash memory circuit, including:

a flash memory array comprising at least a first decode block of flash memory cells, wherein the first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block;
and
disturb count circuitry which generates count signals indicative of a disturb count for each of the erase blocks of the first decode block and which generates from the count signals a set of updated count signals in response to each erasure of at least one of the erase blocks of the first decode block, where each said disturb count is indicative of the disturb effect on a different one of the erase blocks.

A flash memory circuit, including:

a flash memory array comprising at least a first decode block of flash memory cells, wherein the first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block;
a second flash memory array comprising at least a second decode block of flash memory cells, wherein the second decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the second decode block;
and
a controller which controls memory operations of the flash memory array and the second flash memory array including an erasure of any selected one of the erase blocks in a selected decode block, wherein the selected decode block is a selected one of the first decode block and the second decode block, wherein the controller is programmed with software so that said control generates count signals indicative of a disturb count for each of the erase blocks of the selected decode block and processes the count signals to generate a set of updated count signals in response to each erasure of at least one of the erase blocks of said selected decode block.

1 more element

A flash memory circuit, including:

a flash memory array comprising at least one decode block of flash memory cells, wherein each said decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the decode block containing said each of the erase blocks;
a disturb count memory which stores a disturb count table for each said decode block, said disturb count table comprising data indicative of a disturb unit count for each of the erase blocks, where each said disturb unit count is indicative of the disturb effect on a different one of the erase blocks;
and
circuitry which generates the disturb count table and stores said disturb count table in the disturb count memory.

1 more element

A flash memory circuit, including:

a flash memory array comprising at least a first decode block of flash memory cells, wherein the first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block;
and
a controller which controls memory operations of the flash memory array including erasure of at least one of the erase blocks, wherein the controller is programmed with software so that the controller generates count signals indicative of a disturb count for each of the erase blocks of the first disturb block and generates from the count signals a set of updated count signals in response to each erasure of at least one of the erase blocks of the first disturb block, where each said disturb count is indicative of the disturb effect on a different one of the erase blocks, and wherein the controller is also programmed with software so that said controller performs a refresh operation on each of the erase blocks whose disturb unit count reaches a predetermined maximum value,
where the refresh operation includes a step of identifying at least one disturbed cell of said each of the erase blocks whose disturb unit count reaches a predetermined maximum value, where each said disturbed cell has a floating gate which has lost at least a minimum amount of charge due to the disturb effect, and a step of reprogramming each said disturbed cell.

1 more element

A method for monitoring disturb status of erase blocks of a flash memory array, where the array comprises at least a first decode block of flash memory cells, said first decode block includes at least two erase blocks of the cells, each of the erase blocks is independently erasable and includes at least one row of said cells, and each of the erase blocks is subject to a disturb effect due to each erasure of another of the erase blocks in the first decode block, said method including the steps of:

(a) generating count signals indicative of a disturb count for each of the erase blocks of the first disturb block, where each said disturb count is indicative of the disturb effect on a different one of the erase blocks;
(b) generating from the count signals a set of updated count signals in response to each erasure of at least one of the erase blocks of the first disturb block;
and
(c) performing a refresh operation on each of the erase blocks whose disturb unit count reaches a predetermined maximum value.

1 more element

Dependencies are inferred from the claim text.

Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks

Life of this patent

Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks

Life of this patent

Abstract

Claims34