Memory system, control method thereof, and program

A method of controlling a memory device, the memory device including a control circuit configured to execute a plurality of read modes and a nonvolatile memory cell array that includes first memory cells and second memory cells, said method comprising:

• receiving a first read request from a host;
• outputting a first read command, a first physical address, and first information to the memory device, the first physical address corresponding to the first memory cells storing first data that is target data of the first read request, each of the first memory cells storing a first number of bits;
• receiving a second read request from the host;
• and
• outputting a second read command, a second physical address, and second information to the memory device, the second physical address corresponding to the second memory cells storing second data that is target data of the second read request, each of the second memory cells storing a second number of bits, the second number of bits being different from the first number of bits, wherein
• the second information is different from the first information.

A method of controlling a memory device, the memory device including a control circuit configured to execute a plurality of read modes and a nonvolatile memory cell array that includes a plurality of blocks each of which is a unit of a data erase operation, said method comprising:

• receiving a first read request from a host;
• determining, on the basis of whether a first block that is included in the plurality of blocks and stores first read target data of the first read request is in a first state or a second state, a first read instruction to be outputted to the memory device to cause the control circuit to execute one of the plurality of read modes when reading the first read target data;
• and
• outputting the determined first read instruction to the memory device.

A memory system comprising:

• a memory device including a nonvolatile memory cell array and a control circuit configured to execute a plurality of read modes;
• and
• a memory controller configured to:
• receive a read request;
• select, on the basis of an error history regarding read target data of the read request, from the plurality of read modes, a read mode to be executed by the memory device first in a read sequence corresponding to the read request;
• and
• issue a read command to the memory device to cause the control circuit to execute the selected read mode.

A memory system comprising:

• a memory device including a nonvolatile memory cell array and a control circuit configured to execute a plurality of read modes;
• and
• a memory controller configured to:
• receive a read request;
• and
• output a read instruction to the memory device, the read instruction including a first prefix command, a second prefix command, a read command, and a physical address associated with read target data of the read request, wherein
• the first prefix command designates one of the plurality of read modes to be executed when reading the read target data, and
• the second prefix command designates a page type corresponding to the physical address.

A memory device connectable to a memory controller via a bus, comprising:

• a nonvolatile memory cell array that includes first memory cells and second memory cells;
• and
• a control circuit configured to:
• execute a first read mode and a second read mode;
• receive a first read command, a first physical address, and first information from the memory controller through the bus, the first physical address corresponding to the first memory cells storing first data, each of the first memory cells storing a first number of bits;
• in response to receiving the first read command, the first physical address, and the first information from the memory controller, execute the first read mode to read the first data from the first memory cells;
• receive a second read command, a second physical address, and second information from the memory controller through the bus, the second physical address corresponding to the second memory cells storing second data, each of the second memory cells storing a second number of bits, the second number of bits being different from the first number of bits;
• and
• in response to receiving the second read command, the second physical address, and the second information from the memory controller, execute the second read mode to read the second data from the second memory cells, wherein
• the second information is different from the first information.