G11C 16/0458
Comprising two or more independent floating gates which store independent data
Official title: {comprising two or more independent floating gates which store independent data}
G11C16/0458 (Comprising two or more independent floating gates which store independent data) appears on 338 US grants and 286 published applications in this corpus.
Search patents in G11C- Granted patents
- 338
- Published applications
- 286
- Assignees
- 111
- Inventors
- 464
- Latest grant
- 17 Mar 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 1 | 0 |
| 1997 | 2 | 0 |
| 1998 | 11 | 0 |
| 1999 | 8 | 0 |
| 2000 | 6 | 0 |
| 2001 | 17 | 5 |
| 2002 | 13 | 15 |
| 2003 | 19 | 20 |
| 2004 | 16 | 19 |
| 2005 | 24 | 33 |
| 2006 | 16 | 22 |
| 2007 | 25 | 22 |
| 2008 | 17 | 14 |
| 2009 | 12 | 8 |
| 2010 | 14 | 6 |
| 2011 | 4 | 8 |
| 2012 | 6 | 10 |
| 2013 | 12 | 7 |
| 2014 | 7 | 5 |
| 2015 | 8 | 8 |
| 2016 | 12 | 5 |
| 2017 | 9 | 14 |
| 2018 | 14 | 10 |
| 2019 | 16 | 18 |
| 2020 | 14 | 6 |
| 2021 | 5 | 9 |
| 2022 | 3 | 5 |
| 2023 | 7 | 6 |
| 2024 | 8 | 4 |
| 2025 | 3 | 6 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Memory device, memory system, memory controller, and operation method17 Mar 2026US 12,578,899 B2Yangtze Memory Technologies Co., Ltd.
- Memory device and computing method thereof23 Sep 2025US 12,423,375 B2Macronix International Co., Ltd.
- Read latency reduction for partially-programmed block of non-volatile memory15 Jul 2025US 12,362,016 B2Intel NDTM US LLC
- Ternary content addressable memory and decision generation method for the same28 Jan 2025US 12,211,550 B2Macronix International Co., Ltd.
- 3D memory device including shared select gate connections between memory blocks29 Oct 2024US 12,131,782 B2
- Reduced power consumption for programming or erasing a split-gate memory cell, memory cell and manufacturing method22 Jan 2026US 2026/0025992 A1STMicroelectronics International N. V.
- Read latency reduction for partially-programmed block of non-volatile memory6 Nov 2025US 2025/0342886 A1Intel NDTM US LLC
- Memory device, memory system, memory controller, and operation method21 Aug 2025US 2025/0265009 A1Yangtze Memory Technologies Co., Ltd.
- Ternary content addressable memory and decision generation method for the same24 Apr 2025US 2025/0131960 A1Macronix International Co., Ltd.
- 3d memory device including shared select gate connections between memory blocks30 Jan 2025US 2025/0037767 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Multigate semiconductor device with vertical channel current and method of fabrication396US 6,580,124 B1Matrix Semiconductor, Inc. · 2003
- Memory using insulator traps313US 6,545,314 B2Micron Technology, Inc. · 2003
- Multigate semiconductor device with vertical channel current and method of fabrication307US 6,677,204 B2Matrix Semiconductor, Inc. · 2004
- 3D memory array arranged for FN tunneling program and erase301US 8,203,187 B2Macronix International Co., Ltd. · 2012
- Non-volatile semiconductor memory device with facility of storing tri-level data274US 5,021,999 AMitsubishi Denki Kabushiki Kaisha · 1991