US 12,131,782 B2 · 3D memory device including shared select gate connections between memory blocks

Abstract

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Claims20

Dependent claims

A memory device comprising:

a data line;
a first memory cell string coupled to the data line;
a second memory cell string coupled to the data line;
a first access line associated with the first memory cell string;
a second access line associated with the second memory cell string, the second access line electrically separated from the first access line;
a plurality of first select lines associated with the first memory cell string, wherein the plurality of first select lines is configured to selectively electrically couple the data line and the first memory cell string;
a plurality of second select lines associated with the second memory cell string, wherein the plurality of second select lines is configured to selectively electrically couple the data line and the second memory cell string;
and
a conductive connection coupled between one of the plurality of first select lines and one of the plurality of second select lines.

6 more elements

A non-transitory machine-readable medium, storing instructions, which when executed by a memory device, causes the memory device to perform operations comprising:

performing a command operation to a first memory cell string of a plurality of memory cell strings in the memory device by:
turning on a first set of select gates of a plurality of select gates, wherein the plurality of select gates is coupled to a plurality of select lines associated with the plurality of memory cell strings in the memory device, and wherein the plurality of select lines is configured to selectively electrically couple the plurality of memory cell strings to a data line via the plurality of select gates, and wherein the first set of select gates is coupled to a first set of select lines of the plurality of select lines, wherein the first set of select lines is configured to selectively electrically couple the data line and the first memory cell string;
and
turning off a second set of select gates of the plurality of select gates, wherein the second set of select gates is coupled to a second set of select lines of the plurality of select lines, wherein the second set of select lines is configured to selectively electrically couple the data line and a second memory cell string of the plurality of memory cell strings, and wherein a conductive connection is coupled between the first set of select lines and the second set of select lines.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/195,147Filed 9 May 2023 · continuation

Priority

31 Aug 2017

Published

US 2023/0420049 A128 Dec 2023

Granted

29 Oct 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/0458
Comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates:…
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND

Family

Application15/693,118Parent of this continuation · filed 31 Aug 2017

Application16/228,534Parent of this continuation · filed 20 Dec 2018

Application16/921,613Parent of this continuation · filed 6 Jul 2020

Application17/514,899Parent of this continuation · filed 29 Oct 2021

US 2023/0420049 A1Pre-grant publication · published 28 Dec 2023

US 11,670,370 B2Parent of this continuation

US 11,164,629 B2Parent of this continuation

US 10,706,930 B2Parent of this continuation

US 10,170,188 B1Parent of this continuation

US 2019/0147954 A1Published application

US 2020/0357468 A1Published application

US 2022/0051720 A1Published application

US 12,131,782 B2This patent

From the US filing history. Foreign family members aren’t listed.

3D memory device including shared select gate connections between memory blocks

Life of this patent

3D memory device including shared select gate connections between memory blocks

Life of this patent

Abstract

Claims20