Multigate semiconductor device with vertical channel current and method of fabrication

A method of forming a multibit nonvolatile memory comprising:

• forming a first plurality of parallel lines having a top surface and bottom surface, wherein:
• each of the first plurality of parallel lines comprises a first heavily doped semiconductor region of a first conductivity type in a monocrystalline silicon substrate, a second lightly doped semiconductor region of a second conductivity type on the first region and a third heavily doped semiconductor region of the first conductivity type on the second region;
• the top surface comprises a top surface of the respective third heavily doped semiconductor region;
• and
• the bottom surface is the first heavily doped region formed in the monocrystalline silicon substrate;
• forming a first insulating layer on said monocrystalline silicon substrate between said first plurality of parallel lines;
• depositing a first charge storage medium between said first plurality of parallel lines;
• depositing a first control gate film onto said first charge storage medium over and between said first plurality of parallel lines;
• etching back said first control gate film between said first plurality of parallel lines to a level beneath the top surface of said plurality of lines;
• forming a second insulating layer on said etched back first control gate film between said first plurality of lines;
• blanket depositing a polysilicon film over and in contact with said top surface of said first plurality of parallel lines and on said second insulating layer between said first plurality of parallel lines;
• etching said polysilicon film into a second plurality of lines which are perpendicular to said first plurality of parallel lines, and etching a portion of said first plurality of parallel lines not covered by said second plurality of lines to form a plurality of pillars at the intersections of said first and second plurality of lines;
• depositing a second charge storage medium between said second plurality of lines and between said pillars;
• and
• depositing a second control gate material on said second charge storage medium between said second plurality of lines and between said pillars.

A method of fabrication a nonvolatile multibit memory comprising:

• forming a first N+ doped region in a P type silicon substrate;
• growing a P-type silicon film on said first N+ doped region;
• implanting N type impurities into said P-type silicon film to form a second N+ doped region on said P-type silicon film;
• patterning said first N+ doped region, said P-type silicon film, and said second N+ doped region into a first plurality of parallel lines;
• forming a nitride film on the sidewalls of said first plurality of parallel lines;
• oxidizing said substrate to grow an oxide between said first plurality of parallel lines;
• depositing a first charge storage medium over and around and between said first plurality of parallel lines;
• depositing a first control gate material on said first charge storage medium over and around and between said first plurality of parallel lines;
• removing said control gate material between said first plurality of parallel lines to below a top surface of said second N+ doped region;
• blanket depositing an insulating oxide on said control gate material between said first plurality of parallel lines and on said first charge storage medium on said first plurality of parallel lines;
• removing said insulating oxide and said first charge storage medium from the top of said first plurality of parallel lines to expose said second N+ doped region;
• depositing an N+ polysilicon film over and onto said second N+ doped region and over and onto said insulating oxide on said control gate material between said first plurality of parallel lines;
• patterning said N+ polysilicon film into a second plurality of parallel lines wherein said second plurality of parallel lines run orthogonal to said first plurality of parallel lines;
• continuing the patterning of said N+ polysilicon film through said second N+ doped region, said P-type silicon film, and stopping on said first N+ doped region and thereby forming a plurality of N+/P−/N+ pillars at the intersections of said first and second plurality of lines;
• depositing a second charge storage medium over and around said plurality of pillars;
• blanket depositing a second control gate film over said second charge storage medium;
• and
• etching back said second control gate film.

A method of forming a multibit nonvolatile memory comprising:

• forming a first plurality of parallel lines having a top surface and bottom surface, wherein:
• the first plurality of parallel lines comprise a first heavily doped semiconductor region of a first conductivity type in a monocrystalline silicon substrate, a second lightly doped semiconductor region of a second conductivity type on the first region and a third heavily doped semiconductor region of the first conductivity type on the second region;
• the top surface comprises a top surface of the third heavily doped semiconductor region;
• and
• the bottom surface is the first heavily doped region formed in the monocrystalline silicon substrate;
• forming a first oxidation resistant film on the third heavily doped semiconductor region of the first conductivity type in the first plurality of parallel lines;
• forming a second oxidation resistant film on sidewalls of the first plurality of parallel lines;
• selectively oxidizing an exposed portion of the monocrystalline silicon substrate located between the first plurality of parallel lines to form a first insulating layer on said monocrystalline silicon substrate between said first plurality of parallel lines;
• removing the first and the second oxidation resistant films;
• depositing a first charge storage medium between said first plurality of parallel lines;
• depositing a first control gate film onto said first charge storage medium over and between said first plurality of parallel lines;
• etching back said first control gate film between said first plurality of parallel lines to a level beneath the top surface of said first plurality of parallel lines;
• forming a second insulating layer on said etched back first control gate film between said first plurality of parallel lines;
• blanket depositing a polysilicon film over and in contact with said top surface of said first plurality of parallel lines and on said second insulating layer between said first plurality of parallel lines;
• etching said polysilicon film into a second plurality of lines which are perpendicular to said first plurality of parallel lines, and etching a portion of said first plurality of parallel lines not covered by said second plurality of lines to form a plurality of pillars at the intersections of said first and second plurality of lines;
• depositing a second charge storage medium between said second plurality of lines and on exposed portions of the substrate between the plurality of pillars;
• depositing a second control gate material on said second charge storage medium between said second plurality of lines and between said pillars;
• polishing back the second control gate material;
• recessing the second control gate material below the second plurality of lines to form second control gates;
• forming an interlayer dielectric above the second control gates;
• and
• polishing the interlayer dielectric such that it is located planar with the second plurality of lines.

A method of forming a multibit nonvolatile memory comprising:

• forming a plurality of parallel lines, each line comprising a first heavily doped semiconductor region of a first conductivity type, a second lightly doped semiconductor region of a second conductivity type on the first region and a third heavily doped semiconductor region of the first conductivity type on the second region, each of said plurality of parallel lines having a top surface, a bottom and first and second laterally opposite sidewalls;
• forming a first pair of charge storage media adjacent to and in contact with said laterally opposite sidewalls of said plurality of parallel lines;
• forming a first pair of control gates adjacent to said first pair of charge storage media adjacent to said first and second laterally opposite sidewalls;
• patterning said plurality of parallel lines into a plurality of pillars, said pillars having first and second laterally opposite sidewalls;
• forming a second pair of charge storage media adjacent to and in contact with said laterally opposite sidewalls of said pillars and on exposed portions of a substrate between the plurality of pillars;
• and
• forming a second pair of control gates adjacent to and in contact with said second pair of charge storage media and on the second pair of charge storage media located on exposed portions of the substrate between the plurality of pillars.