Read latency reduction for partially-programmed block of non-volatile memory

A computer-implemented method comprising, in a processor of a memory device, logic for:

• identifying one or more vulnerable wordlines in the memory device likely to result in an unsuccessful read operation, wherein the one or more vulnerable wordlines are any one or more of:
• located in a partially-programmed block, including at least one wordline most recently programmed in the partially-programmed block, and
• characterized by a lack of floating-gate to floating-gate coupling as a result of having been programmed in the partially-programmed block;
• selecting a read offset voltage value for a read operation in the memory device;
• causing the memory device to proactively adjust a read voltage with the read offset voltage value prior to performance of the read operation on any of the one or more vulnerable wordlines;
• causing the memory device to perform the read operation on any of the one or more vulnerable wordlines with an adjusted read voltage;
• and
• wherein the logic for identifying the one or more vulnerable wordlines likely to result in an unsuccessful read operation includes:
• tracking wordline offsets associated with past unsuccessful read operations on wordlines programmed in a partially-programmed block,
• determining a wordline-specific pattern of tracked wordline offsets associated with past unsuccessful read operations, and
• identifying wordlines matching the wordline-specific pattern of tracked wordline offsets as vulnerable wordlines in advance of a read operation in the memory device.

A system comprising:

• a memory device comprising block-addressable non-volatile memory;
• and
• a processor communicatively coupled to the memory device, the processor to execute logic to:
• identify one or more vulnerable wordlines in the at least one or more memory devices likely to result in an unsuccessful read operation, wherein the one or more vulnerable wordlines are located in a partially-programmed block of the block-addressable non-volatile memory, including at least one wordline most recently programmed in the partially-programmed block characterized by a lack of floating-gate to floating-gate coupling as a result of having been programmed in the partially-programmed block,
• select a read offset voltage value for a read operation in the memory device,
• cause the memory device to proactively adjust a read voltage with the read offset voltage value prior to performance of the read operation on any of the one or more vulnerable wordlines, and
• cause the memory device to perform the read operation on any of the one or more vulnerable wordlines with an adjusted read voltage;
• and
• wherein, to proactively adjust a read voltage with the read offset voltage value, the processor to execute logic to:
• generate a command to a memory device to adjust the read voltage, the command including the read offset voltage value, including a trim command to adjust the read voltage based on a trim profile stored in the memory device,
• transmit the command to the memory device prior to performance of the read operation on any of the one or more vulnerable wordlines, and
• cause the memory device to restore the read voltage to an unadjusted read voltage after performance of the read operation on any of the one or more vulnerable wordlines.

A non-transitory machine-readable tangible storage medium, comprising a plurality of instructions executable by a system to cause the system to:

• identify one or more vulnerable wordlines in a memory device likely to result in an unsuccessful read operation, the one or more vulnerable wordlines located in a partially-programmed block of non-volatile memory in the memory device, including at least one wordline most recently programmed in the partially-programmed block characterized by a lack of floating-gate to floating-gate coupling as a result of having been programmed in a partially-programmed block;
• select a read offset voltage value for a read operation in the memory device;
• cause the memory device to proactively adjust a read voltage with the read offset voltage value prior to performance of the read operation on any of the one or more vulnerable wordlines;
• cause the memory device to perform the read operation on any of the one or more vulnerable wordlines with an adjusted read voltage;
• and
• wherein to identify the one or more vulnerable wordlines likely to result in an unsuccessful read operation, the plurality of instructions cause the system to:
• track wordline offsets associated with past unsuccessful read operations on wordlines programmed in a partially-programmed block,
• determine a wordline-specific pattern of tracked wordline offsets associated with past unsuccessful read operations, and
• identify wordlines matching the wordline-specific pattern of tracked wordline offsets as vulnerable wordlines in advance of a read operation in the memory device.