Reduced power consumption for programming or erasing a split-gate memory cell, memory cell and manufacturing method
AssigneeSTMicroelectronics International N.V.
InventorChristian RIVERO
Life of this patent
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Abstract
A non-volatile memory device includes a memory cell having a split gate state transistor and a vertical type select transistor buried in a semiconductor substrate. The memory device includes structure designed to increase the mobility of the carriers in a semiconductor channel of the vertical type select transistor during a programming or erasing operation of the memory cell by hot carriers.
Claims26
A non-volatile memory device, comprising:
- a memory cell having a split gate state transistor and a vertical type select transistor buried in a semiconductor substrate;
- and
- means for increasing mobility of carriers in a semiconductor channel of the vertical type select transistor during a programming or erasing operation of the memory cell by hot carriers.
A non-volatile memory device, comprising:
- a first memory cell having a split gate state transistor and a vertical type select transistor buried in a semiconductor substrate;
- wherein the vertical type select transistor has a semiconductor channel having a silicon region located between a gate oxide region and a region of a silicon germanium alloy.
A method for reducing power consumption during a programming or erasing operation by hot carriers of a memory cell having a split gate state transistor and a vertical type select transistor buried in a semiconductor substrate, the method comprising increasing mobility of carriers in semiconductor channel of the vertical type select transistor during said programming or erasing operation.
A method for manufacturing a non-volatile memory device, comprising producing a non-volatile memory cell by:
- producing in and on a semiconductor substrate a split gate state transistor;
- and
- producing a vertical type select transistor buried in the semiconductor substrate;
- wherein producing the vertical type select transistor comprises:
- forming a trench in the semiconductor substrate;
- epitaxially growing a layer of a silicon germanium alloy on walls of the trench;
- epitaxially growing a silicon layer on the layer of said silicon germanium alloy;
- forming a gate oxide layer on the silicon layer;
- and
- filling the trench with polysilicon so as to form a gate region of the select transistor.
Dependencies are inferred from the claim text.