Memory device and computing method thereof

A memory device, comprising:

• a memory array, for processing a model computation, wherein the model computation has a plurality of input-values, a plurality of self-coefficients, a plurality of mutual-coefficients and a plurality of output-values, and the memory array comprises:
• a plurality of first-word-lines and a plurality of second-word-lines;
• a plurality of first-bit-lines and a plurality of second-bit-lines;
• a plurality of common-source-lines;
• and
• a plurality of memory cells, wherein the plurality of memory cells respectively receive the plurality of input-values through the plurality of first-word-lines, receive inverted logic values of the plurality of input-values through the plurality of second-word-lines, receive the plurality of input-values through the plurality of first-bit-lines, and receive the inverted logic values through the plurality of second-bit-lines and output the plurality of output-values through the plurality of common-source-lines,
• wherein each of the plurality of memory cells performs a logic XNOR operation according to each of the plurality of input-values and each of the inverted logic values to obtain a first computation result, and multiplies the first computation result by one of the plurality of self-coefficients or one of the plurality of mutual-coefficients to obtain each of the plurality of output-values.