3D memory array arranged for FN tunneling program and erase

A memory device including a 3D array of memory cells, comprising:

• an integrated circuit substrate;
• an array of semiconductor body pillars and bit line pillars on the substrate arranged to intersect a plurality of word line levels including word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars, the semiconductor body pillars in the array having corresponding bit line pillars on opposing first and second sides, and having first and second channel surfaces on opposing third and fourth sides;
• dielectric charge trapping structures on the first and second channel surfaces of the semiconductor body pillars in the array;
• the word line structures in the plurality of levels respectively having a first set of word lines arranged adjacent the dielectric charge trapping structures on semiconductor body pillars in the array and a second set of word lines arranged adjacent the dielectric charge trapping structures on semiconductor body pillars in the array;
• the bit line pillars in the array including bottom-decoded pillars on said first sides of the semiconductor body pillars and top-decoded pillars on said second sides of the semiconductor body pillars;
• decoder circuitry coupled to the array of semiconductor body pillars and bit line pillars, to the levels of word line structures, arranged to access selected memory cells in the 3D array;
• and
• a controller arranged to program and erase selected memory cells in the 3D array by biasing the corresponding semiconductor body pillars and one of the first or second sets of word lines in the corresponding level, and to read selected memory cells in the 3D array by sensing current in bit line pillars on opposing sides of corresponding semiconductor body pillars in response to gate voltages applied to one of the first or second sets of word lines in the corresponding level.

A method for manufacturing a memory device, comprising:

• forming a plurality of two-cell structures arranged in three dimensions, the two cell structures including a semiconductor body pillar, first and second bit line pillars on opposing first and second sides of the semiconductor body pillar, dielectric charge trapping structures on third and fourth opposing sides of the semiconductor body pillar, a first word line arranged adjacent the dielectric charge trapping structure on the third side of the semiconductor body pillar and a second word line arranged adjacent the dielectric charge trapping structure on the fourth side of the semiconductor body pillar;
• said just mentioned forming including:
• providing a substrate including an array of access devices and a first set of bit lines, the substrate having a surface with an array of contacts, including contacts coupled to access devices in the array of access devices and contacts coupled to bit lines in the set of bit lines;
• forming a stack of alternating layers of word line material and insulating material over the array of contacts;
• forming trenches in the stack, the trenches exposing respective rows of contacts on the surface of the substrate coupled to access devices and exposing contacts on the surface of the substrate coupled to bit lines in the first set of bit lines, and having sidewalls exposing word line material in the layers of word line material in the stack;
• forming a charge trapping structure, lining the sidewalls of the trenches at least on word line material exposed on sidewalls of the trenches;
• forming semiconductor body pillars within the trenches over the charge trapping structure, the semiconductor body pillars contacting respective contacts in the rows of contacts in the trenches;
• forming bit line pillars within the trenches on first and second opposing sides of the semiconductor body pillars and within the trenches, where bit line pillars on the first side of the semiconductor body pillars contact respective contacts coupled to a bit line in the first set of bit lines;
• and
• forming a second set of bit lines coupled to the bit line pillars on the second opposing side of the semiconductor body pillars;
• and
• forming a controller arranged to program and erase selected memory cells in the plurality of two-cell structures by biasing corresponding semiconductor body pillars and one of the first or second word lines to induce Fowler-Nordheim tunneling.