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US 6,580,124 B1Granted
Multigate semiconductor device with vertical channel current and method of fabrication
AssigneeMatrix Semiconductor, Inc.
InventorsJames M. Cleeves, Vivek Subramanian
Life of this patent
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Abstract
The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.
Claims19
A multibit nonvolatile pillar memory comprising:
- a pillar comprising:
- a first source/drain region of a first conductivity type;
- a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region;
- a second source/drain region of the first conductivity type formed on the channel region;
- wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;
- a charge storage medium comprising nanocrystals formed adjacent to each of said first, second, third and forth face of said pillar;
- a first control gate adjacent to said charge storage medium adjacent to said first face;
- a second control gate adjacent to said charge storage medium adjacent to said second face;
- a third control gate adjacent to said charge storage medium adjacent to said third face;
- and
- a fourth control gate adjacent to said charge storage medium adjacent to said fourth face.
8 more elements
A multibit nonvolatile pillar memory comprising:
- a pillar comprising:
- a first source/drain region of a first conductivity type;
- a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region;
- a second source/drain region of the first conductivity type formed on the channel region;
- wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;
- a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar;
- a first control gate adjacent to said charge storage medium adjacent to said first face;
- a second control gate adjacent to said charge storage medium adjacent to said second face;
- a third control gate adjacent to said charge storage medium adjacent to said third face;
- and
- a fourth control gate adjacent to said charge storage medium adjacent to said fourth face;
- and
- wherein said charge storage medium is an oxide with H+ ions therein.
10 more elements
A multibit nonvolatile pillar memory comprising:
- a pillar comprising:
- a first source/drain region;
- a channel region formed on the first source/drain region;
- second source/drain region formed on the channel region;
- wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face
- and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;
- a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar;
- a first control gate adjacent to said charge storage medium adjacent to said first face;
- a second control gate adjacent to said charge storage medium adjacent to said second face;
- a third control gate adjacent to said charge storage medium adjacent to said third face;
- a fourth control gate adjacent to said charge storage medium adjacent to said fourth face;
- and
- wherein the channel region of said first face and the channel region of said third face have a different doping density;
- and
- the charge storage medium comprises nanocrystals.
12 more elements
A multibit nonvolatile memory comprising:
- a first source/drain region of a first conductivity type;
- a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region,
- a second source/drain region of the first conductivity type on said channel region;
- a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface, wherein the first, the second and the third charge storage medium comprise nanocrystals;
- a first control gate adjacent to said first charge storage medium adjacent to said first channel surface;
- a second control gate adjacent to said second charge storage medium adjacent to said second channel surface;
- and
- a third control gate adjacent to said third charge storage medium adjacent to said third channel surface.
5 more elements
A multibit nonvolatile memory comprising:
- a first source/drain region of a first conductivity type;
- a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region,
- a second source/drain region of the first conductivity type on said channel region;
- a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface;
- a first control gate adjacent to said first charge storage medium adjacent to said first channel surface;
- a second control gate adjacent to said second charge storage medium adjacent to said second channel surface;
- and
- a third control gate adjacent to said third charge storage medium adjacent to said third channel surface;
- and
- wherein said first, second and third charge storage medium is an oxide with H+ ions therein.
7 more elements
A multibit nonvolatile pillar memory comprising:
- a pillar comprising:
- a first source/drain region;
- a channel region formed on the first source/drain region;
- a second source/drain region formed on the channel region;
- wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;
- a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar;
- a first control gate adjacent to said charge storage medium adjacent to said first face;
- a second control gate adjacent to said charge storage medium adjacent to said second face;
- a third control gate adjacent to said charge storage medium adjacent to said third face;
- a fourth control gate adjacent to said charge storage medium adjacent to said fourth face;
- and
- wherein the channel region of said first face and the channel region of said third face have a different doping density;
- and
- said charge storage medium comprises an oxide with H+ ions therein.
11 more elements
A multibit nonvolatile memory comprising:
- a first source/drain region;
- a channel region having a first and a second channel surface formed on said first source/drain region, wherein a first portion of the channel region adjacent to said first surface, and a second portion of the channel region adjacent to second surface have a different doping density;
- a second source/drain region on said channel region;
- a first charge storage medium adjacent to said first channel surface and a second charge storage medium adjacent to said second channel surface, wherein the first and the second charge storage medium comprise nanocrystals or an oxide with H+ ions therein;
- a first control gate adjacent to said first charge storage medium adjacent to said first channel surface;
- and
- a second control gate adjacent to said second charge storage medium adjacent to said second channel surface.
4 more elements
Dependencies are inferred from the claim text.