G06F 7/501
Half or full adders, i.e. basic adder cells for one denomination
G06F7/501 (Half or full adders, i.e. basic adder cells for one denomination) appears on 505 US grants and 328 published applications in this corpus.
Search patents in G06F- Granted patents
- 505
- Published applications
- 328
- Assignees
- 228
- Inventors
- 922
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 5 | 0 |
| 1977 | 4 | 0 |
| 1978 | 2 | 0 |
| 1979 | 8 | 0 |
| 1980 | 3 | 0 |
| 1981 | 1 | 0 |
| 1982 | 3 | 0 |
| 1983 | 4 | 0 |
| 1984 | 9 | 0 |
| 1985 | 7 | 0 |
| 1986 | 11 | 0 |
| 1987 | 6 | 0 |
| 1988 | 10 | 0 |
| 1989 | 13 | 0 |
| 1990 | 10 | 0 |
| 1991 | 10 | 0 |
| 1992 | 8 | 0 |
| 1993 | 9 | 0 |
| 1994 | 9 | 0 |
| 1995 | 8 | 0 |
| 1996 | 11 | 0 |
| 1997 | 11 | 0 |
| 1998 | 8 | 0 |
| 1999 | 12 | 0 |
| 2000 | 11 | 0 |
| 2001 | 15 | 5 |
| 2002 | 9 | 4 |
| 2003 | 8 | 10 |
| 2004 | 7 | 6 |
| 2005 | 3 | 6 |
| 2006 | 5 | 8 |
| 2007 | 12 | 3 |
| 2008 | 6 | 5 |
| 2009 | 5 | 3 |
| 2010 | 6 | 5 |
| 2011 | 5 | 4 |
| 2012 | 4 | 3 |
| 2013 | 3 | 2 |
| 2014 | 6 | 5 |
| 2015 | 2 | 2 |
| 2016 | 5 | 9 |
| 2017 | 9 | 3 |
| 2018 | 7 | 20 |
| 2019 | 9 | 23 |
| 2020 | 23 | 17 |
| 2021 | 14 | 26 |
| 2022 | 42 | 39 |
| 2023 | 26 | 38 |
| 2024 | 30 | 32 |
| 2025 | 32 | 32 |
| 2026 | 19 | 18 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Syndrome decoding system15 Sep 2026US 12,737,257 B2Micron Technology, Inc.
- Machine learning hardware accelerator8 Sep 2026US 12,731,067 B2Texas Instruments Incorporated
- Memory system and memory die with cascaded calculating circuits1 Sep 2026US 12,725,641 B2Nanya Technology Corporation
- Method of forming a majority gate based low power ferroelectric based adder with reset mechanism30 Jun 2026US 12,671,420 B2Kepler Computing Inc.
- Scalar masking countermeasure23 Jun 2026US 12,664,259 B2Microsoft Technology Licensing, LLC
- Control method and apparatus for non-volatile majority gate circuit and adder circuit based on memristors1 Oct 2026US 2026/0299883 A1Huazhong University of Science and Technology
- Direct memory access circuit with masking conversions3 Sep 2026US 2026/0259844 A1
- Circuit of adder tree and method of operating the same20 Aug 2026US 2026/0244400 A1National Tsing Hua University
- Full adder and full adder trees implementing negative outputs13 Aug 2026US 2026/0236227 A1Taiwan Semiconductor Manufacturing Company.Ltd
- High-speed selective carry propagate adder13 Aug 2026US 2026/0236721 A1Indian Institute of Technology Madras (Iit Madras)
Most cited
By later US patents
- Logic structure and circuit for fast carry322US 5,349,250 AXilinx, Inc. · 1994
- Logic circuit and full adder using the same181US 6,700,405 B1Sony Corporation · 2004
- Fast carry structure with synchronous input159US 5,546,018 AXilinx, Inc. · 1996
- Logic structure and circuit for fast carry138US 5,267,187 A1993
- Look up table implementation of fast carry for adders and counters136US 5,274,581 AAltera Corporation · 1993