Direct memory access circuit with masking conversions

An electronic system (8) for implementing a post-quantum cryptographic algorithm, the system comprising:

• a communication bus;
• a direct memory access circuit;
• a computing and processing unit, such as a microprocessor, connected to the bus;
• and
• two peripherals connected to the bus each by a slave interface,
• wherein the direct memory access circuit comprises:
• a slave interface configured to receive programming data for programming the direct memory access circuit;
• a master interface connected to the bus and comprising an input port configured to read input data for the direct access memory circuit from a source memory, and an output port configured to write output data of the direct access memory circuit to a destination memory;
• and
• at least one data path coupling the input port to the output port, the at least one data path has a pipelined structure that alternates combinatory stages and memorization registers, and comprises a first data path, the first data path comprises a first circuit configured to apply one among a Boolean to arithmetic masking conversion and an arithmetic to Boolean masking conversion to data propagated by the first data path,
• wherein the computing and processing unit is configured to provide programming data to the slave interface of the direct memory access circuit, the programming data configuring a data transfer by the direct access memory circuit from one of the two peripherals to another of the two peripherals;
• wherein the two peripherals are two hardware accelerators each implementing a cryptographic operation, or are a memory and a hardware accelerator implementing a cryptographic operation;
• and
• wherein one of the two peripheral corresponds to the source memory and the other of the two peripheral corresponds to the destination memory.