Full adder and full adder trees implementing negative outputs

A multiply-accumulate (MAC) circuit, comprising:

• a multiplier circuit configured to generate a plurality of partial products;
• and
• an adder tree circuit configured to:
• receive the plurality of partial products;
• generate an intermediate sum that is logically inverted relative to a first corresponding sum of at least two of the plurality of partial products;
• and
• generate an output sum based on the intermediate sum and a second operand, wherein the output sum is logically inverted relative to a second corresponding sum of the first intermediate sum and the second operand.

A method, comprising:

• receiving, by a first adder circuit of an adder tree circuit, a first operand and a second operand as input;
• generating, by the first adder circuit, a negative sum value, wherein the negative sum value is a logical inversion of a sum of the first operand and the second operand;
• receiving, by a second adder circuit of the adder tree circuit, the negative sum value and a second value as input;
• and
• generating, by the second adder circuit, a positive sum value as output, wherein the positive sum value is equal to the sum of the first operand and the second operand plus a logical inversion of the second value.