Logic circuit and full adder using the same

A logic circuit, comprising:

• an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal,
• a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal,
• an interpolation circuit for compulsorily setting the output level of said exclusive-OR at the second level when the output level of said dual signal is the first level, and
• circuit means coupled to said interpolation circuit for providing an adding function.

A logic circuit, comprising:

• an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal,
• a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal,
• an interpolation circuit for compulsorily setting an output level of said dual signal at the first level when the output level of said exclusive-OR is the second level, while compulsorily setting an output level of said exclusive-OR at the second level when the output level of said dual signal is the first level, and
• circuit means coupled to said interpolation circuit for providing an adding function.

A logic circuit, comprising:

• a first input terminal with a first logic signal taking a first or second level input thereto,
• a second input terminal with a second logic signal taking a first or second level input thereto,
• a first output terminal for outputting an exclusive-OR,
• a second output terminal for outputting a dual signal of said exclusive-OR,
• a dual signal generation circuit having
• first conductivity type first and second transistors connected in series between said first level use power supply potential and said second output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied,
• a second conductivity type first transistor connected between said first input terminal and said second output terminal, turning ON when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, and
• a second conductivity type second transistor connected between said second input terminal and said second output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied,
• an exclusive-OR generation circuit having
• a first conductivity type third transistor connected between said first input terminal and said first output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied,
• a first conductivity type fourth transistor connected between said second input terminal and said first output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and
• second conductivity type third and fourth transistors connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, and
• an interpolation circuit having
• a first conductivity type fifth transistor connected in series between said first level use power supply potential and said second output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and
• a second conductivity type fifth transistor connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, wherein
• the control terminals of said first conductivity type second and fourth transistors and second conductivity type second and third transistors are connected to said first input terminal,
• the control terminals of said first conductivity type first and third transistors and second conductivity type first and fourth transistors are connected to said second input terminal,
• the control terminal of said first conductivity type fifth transistor is connected to said first output terminal,
• the control terminal of said second conductivity type fifth transistor is connected to said second output terminal, and
• circuit means coupled to said interpolation circuit for providing an adding function.

A full adder, comprising:

• a logic circuit having
• an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal,
• a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the related first logic signal and second logic signal, and
• an interpolation circuit for compulsorily setting an output level of said dual signal at the first level when the output level of said exclusive-OR is the second level,
• a sum signal generation circuit for generating a sum signal based on an exclusive-OR output and a dual signal output of said logic circuit, and
• a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.

A full adder, comprising:

• a logic circuit having
• an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal, a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and
• an interpolation circuit for compulsorily setting the output level of said exclusive-OR at the second level when the output level of said dual signal is the first level;
• a sum signal generation circuit for generating a sum signal based on then exclusive-OR output and the dual signal output of said logic circuit;
• and
• a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.

A full adder, comprising

• a logic circuit having
• an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal,
• a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and
• an interpolation circuit for compulsorily setting an output level of said dual signal at the first level when the output level of said exclusive-OR is the second level, while compulsorily setting the output level of said exclusive-OR at the second level when the output level of said dual signal is the first level;
• a sum signal generation circuit for generating a sum signal based on an exclusive-OR output and a dual signal output of said logic circuit;
• and
• a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.

A full adder, comprising:

• a logic circuit having
• a first input terminal with a first logic signal taking a first or second level input thereto,
• a second input terminal with a second logic signal taking a first or second level input thereto,
• a first output terminal for outputting an exclusive-OR,
• a second output terminal for outputting a dual signal of said exclusive-OR,
• a dual signal generation circuit which has
• first conductivity type first and second transistors connected in series between said first level use power supply potential and said second output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied,
• a second conductivity type first transistor connected between said first input terminal and said second output terminal, turning ON when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, and
• a second conductivity type second transistor connected between said second input terminal and said second output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied,
• an exclusive-OR generation circuit which has
• a first conductivity type third transistor connected between said first input terminal and said first output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied,
• a first conductivity type fourth transistor connected between said second input terminal and said first output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and
• second conductivity type third and fourth transistors connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, and
• an interpolation circuit which has
• a first conductivity type fifth transistor connected in series between said first level use power supply potential and said second output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and
• a second conductivity type fifth transistor connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, wherein
• the control terminals of said first conductivity type second and fourth transistors and second conductivity type second and third transistors are connected to said first input terminal,
• the control terminals of said first conductivity type first and third transistors and second conductivity type first and fourth transistors are connected to said second input terminal,
• the control terminal of said first conductivity type fifth transistor is connected to said first output terminal, and
• the control terminal of said second conductivity type fifth transistor is connected to said second output terminal;
• a sum signal generation circuit for generating a sum signal based on an exclusive-OR output and a dual signal output of said logic circuit;
• and
• a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.