Fast carry structure with synchronous input

Abstract

Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions. In some embodiments, the circuit also includes structures which allow efficient implementation of a loadable counter and related applications.

Dependencies are inferred from the claim text.