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US 12,737,257 B2Granted
Syndrome decoding system
AssigneeMicron Technology, Inc.
InventorsLeon Zlotnik, Eyal En Gad, Fan Zhou
Life of this patent
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Abstract
A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
Claims20
A method, comprising:
- determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one or a logical value of zero, or both, within the bit string;
- writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells;
- determining whether the quantity of errors for the bit string has reached a threshold quantity of errors prior to writing the bit string to the array of memory cells;
- responsive to a determination that the quantity of errors for the bit string has reached the threshold quantity of errors, refraining from performing a subsequent operation to correct the quantity of errors for the bit string;
- and
- responsive to a determination that the quantity of errors for the bit string has not reached the threshold quantity of errors:
- responsive to the quantity of errors for the bit string being equal to zero, refraining from performing the subsequent operation to correct the quantity of errors for the bit string and causing the bit string to be written to the array of memory cells;
- and
- responsive to the quantity of errors for the bit string not being equal to zero, performing the subsequent operation to correct the quantity of errors for the bit string and causing the corrected bit string to be written to the array of memory cells.
6 more elements
An apparatus, comprising:
- a first array of memory cells configured to store a plurality of syndromes that each comprise a plurality of bits of data;
- first circuitry coupled to the first array and comprising a multiplexer configured to selectively transfer one or more of the plurality of syndromes to decision circuitry, the decision circuitry configured to determine a quantity of errors contained within each of the syndromes based on a quantity of bits having a logical value of one within each of the syndromes;
- and
- second circuitry coupled to the first circuitry and configured to, for each of the syndromes:
- determine whether each of the syndromes has been fully decoded;
- responsive to a determination that at least one of the syndromes has been fully decoded:
- write an indication, corresponding to the at least one of the fully decoded syndromes, to a second array of memory cells;
- avoid further processing of the at least one of the fully decoded syndromes;
- and
- refrain from performing a subsequent operation to determine the quantity of errors contained within the at least one of the fully decoded syndromes;
- and
- responsive to a determination that at least one of the syndromes has not been fully decoded:
- responsive to determining that the quantity of errors for the syndromes not fully decoded has reached a threshold quantity of errors, refrain from performing a subsequent operation to determine the quantity of errors contained within the syndromes not fully decoded.
10 more elements
A system, comprising:
- a first array of memory cells configured to store a plurality of syndromes that each comprise a plurality of bits of data;
- shift circuitry configured to, for each of the plurality of syndromes, transfer the plurality of bits of data for each of the syndromes to decision circuitry coupled to the shift circuitry, wherein the decision circuitry is configured to determine a quantity of errors contained within each of the syndromes based on a quantity of bits having a logical value of one within each of the syndromes;
- adder circuitry coupled to the decision circuitry, wherein the adder circuitry is configured to:
- sum the quantity of bits having the logical value of one within each of the syndromes to generate a decoding completion indication for each of the syndromes;
- and
- determine, based on the decoding completion indication, that the quantity of errors for the syndromes has reached a threshold quantity of errors, and wherein the decision circuitry is configured to refrain from performing a subsequent operation to determine the quantity of errors contained within the at least one of the syndromes in response to the determination that the quantity of errors contained within the syndromes has reached the threshold quantity of errors, the decision circuitry to refrain from performing the subsequent operation by:
- removing power supplied to a portion of the first memory array that stored the at least one of the syndromes.
4 more elements
Dependencies are inferred from the claim text.