Machine learning hardware accelerator
AssigneeTexas Instruments Incorporated
InventorsMahesh Madhukar Mehendale, Vinod Joseph Menezes
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Abstract
In a memory device, a static random access memory (SRAM) circuit includes an array of SRAM cells arranged in rows and columns and configured to store data. The SRAM array is configured to: store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells. A memory controller circuit is configured to select the set of the SRAM cells based on a second set of information for the ML process.
Claims26
A circuit, comprising:
- a static random access memory (SRAM) circuit including an array of SRAM cells and configurable to store a mapping table;
- and
- a memory controller circuit coupled to the array of SRAM cells and configurable to:
- receive first data;
- responsive to receiving the first data, select multiple SRAM cells from the array of SRAM cells between two precharge operations of bit lines of the array of SRAM cells;
- and
- provide second data from the selected SRAM cells, in which the second data represent results of operations on the first data.
A system, comprising:
- a processor;
- a memory circuit coupled to the processor, the memory circuit including:
- a static random access memory (SRAM) circuit including an array of SRAM cells and configurable to store first data for a machine learning (ML) process;
- and
- a memory controller circuit coupled to the array of SRAM cells and configurable to:
- receive second data from the processor;
- responsive to receiving second data, select multiple SRAM cells from the array of SRAM cells between two precharge operations of bit lines of the array of SRAM cells;
- and
- provide third data from the selected SRAM cells, in which the third data is a subset of the first data and represent results of operations on the second data.
A method, comprising:
- storing a mapping table in an array of SRAM cells;
- receiving first data;
- responsive to receiving the first data, selecting multiple SRAM cells from the array of SRAM cells between two precharge operations of bit lines of the array of SRAM cells;
- and
- providing second data from the selected SRAM cells, in which the second data represent results of operations on the first data.
Dependencies are inferred from the claim text.