Control method and apparatus for non-volatile majority gate circuit and adder circuit based on memristors

A control method of an adder circuit, for implementing an addition operation of n-bit numbers an . . . a2a1 and bn . . . b2b1, wherein the adder circuit comprises a voltage comparator, a resistor, and five memristors, negative terminals of the five memristors are all connected to one end of the resistor, the other end of the resistor is grounded, a first input terminal of the voltage comparator is connected to a common node of the five memristors and the resistor, a resistance value of the resistor is a low resistance state resistance value of the memristors, and n≥1,

• the control method comprises:
• executing n rounds of addition sub-processes;
• wherein in an ith round addition sub-process, the following operations are executed:
• selecting three memristors denoted as a first memristor, a second memristor, and a third memristor, writing a logic value ai into the first memristor, writing a logic value bi into the second memristor, and writing a carry ci of the ith round addition into the third memristor;
• applying a voltage V1 to positive terminals of the first memristor, the second memristor, and the third memristor, connecting a reference voltage VRef1 to a second input terminal of the voltage comparator, and obtaining a result of a majority gate logic operation M(ai, bi, ci) =ai·bi +ai·ci +bi·ci at an output terminal of the voltage comparator as a carry ci+1 of an (i+1)th round addition;
• applying a voltage V2 to the positive terminals of the first memristor and the second memristor, applying a voltage with an amplitude of 0 to the positive terminal of the third memristor, connecting a reference voltage VRef2 to the second input terminal of the voltage comparator, and obtaining a result of a majority gate logic operation M(ai, bi, ci)=ai·bi+ai·ci+bi·ci at the output terminal of the voltage comparator;
• denoting the remaining two unset memristors as a fourth memristor and a fifth memristor, writing M(ai, bi, ci) into the fourth memristor, and writing M(ai, bi, ci) into the fifth memristor;
• and
• applying the voltage V2 to positive terminals of the third memristor and the fifth memristor, applying a voltage with an amplitude of 0 to a positive terminal of the fourth memristor, connecting the reference voltage VRef2 to the second input terminal of the voltage comparator, and obtaining a result of a majority gate logic operation M(ci, M(ai, bi, ci), M(ai, bi, ci)) at the output terminal of the voltage comparator as a summation result si of the ith round addition,
• wherein sn . . . s2s1 and cn+1 are an addition result of the desired n-bit numbers an . . . a2a1 and bn . . . b2b1,
• wherein i=1, 2, . . . , n, 0<V1<Vset, V1/2<VRef1<2V1/3, 0<V2<Vset, and V2/3<VRef2<V2/2, Vset is a threshold for each memristor to transition from a high resistance state to a low resistance state, when a voltage at the first input terminal of the voltage comparator is greater than a voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as a result “1” of the majority gate logic operation;
• otherwise, the output terminal outputs a second level, and the second level is used as a result “0” of the majority gate logic operation.