G06F 7/5016
Forming at least one of the output signals directly from the minterms
Official title: {forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels}
G06F7/5016 (Forming at least one of the output signals directly from the minterms) appears on 60 US grants and 20 published applications in this corpus.
Search patents in G06F- Granted patents
- 60
- Published applications
- 20
- Assignees
- 40
- Inventors
- 110
- Latest grant
- 10 Nov 2020
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 2 | 0 |
| 1986 | 4 | 0 |
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 4 | 0 |
| 1992 | 1 | 0 |
| 1993 | 2 | 0 |
| 1994 | 2 | 0 |
| 1995 | 4 | 0 |
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 2 | 0 |
| 1999 | 3 | 0 |
| 2000 | 3 | 0 |
| 2001 | 4 | 0 |
| 2002 | 0 | 1 |
| 2003 | 2 | 3 |
| 2004 | 1 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 1 |
| 2007 | 1 | 1 |
| 2008 | 1 | 2 |
| 2009 | 0 | 0 |
| 2010 | 2 | 2 |
| 2011 | 2 | 1 |
| 2012 | 1 | 1 |
| 2013 | 1 | 0 |
| 2014 | 1 | 1 |
| 2015 | 0 | 1 |
| 2016 | 1 | 1 |
| 2017 | 2 | 2 |
| 2018 | 2 | 0 |
| 2019 | 0 | 2 |
| 2020 | 2 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 0 |
| 2025 | 0 | 0 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Digital bit-serial multi-multiply-and-accumulate compute in memory10 Nov 2020US 10,831,446 B2Intel Corporation
- Performance power optimized full adder7 Apr 2020US 10,613,829 B2QUALCOMM Incorporated
- Arithmetic circuit and method of driving the same2 Oct 2018US 10,090,333 B2Semiconductor Energy Laboratory Co.Ltd.
- Checksum adder27 Mar 2018US 9,928,032 B2International Business Machines Corporation
- Checksum adder19 Sep 2017US 9,766,859 B2International Business Machines Corporation
- Ultra-high speed full adder (fa) and carry generator circuit18 Jun 2026US 2026/0169694 A1Samsung Electronics Co., Ltd.
- Performance power optimized full adder21 Nov 2019US 2019/0354347 A1QUALCOMM Incorporated
- Digital bit-serial multi-multiply-and-accumulate compute in memory28 Feb 2019US 2019/0065151 A1Intel Corporation
- Checksum adder21 Dec 2017US 2017/0364328 A1International Business Machines Corporation
- Checksum adder23 Feb 2017US 2017/0052763 A1International Business Machines Corporation
Most cited
By later US patents
- X.times.Y Bit array multiplier/accumulator circuit101US 4,575,812 AMotorola, Inc. · 1986
- Clocking systems and methods for pipelined self-timed dynamic logic circuits67US 5,434,520 AHewlett-Packard Company · 1995
- Functionally complete family of self-timed dynamic logic circuits52US 5,208,490 AHewlett-Packard Company · 1993
- Adder-rounder circuitry for specialized processing block in programmable logic device40US 7,822,799 B1Altera Corporation · 2010
- Dynamic logic circuit including bipolar transistors and field-effect transistors36US 4,849,658 AHitachi, Ltd. · 1989