X.times.Y Bit array multiplier/accumulator circuit

An X.times.Y bit array multiplier/accumulator circuit, for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers, to provide an accumulated product, comprising:

• encoding means for implementing a predetermined algorithm and providing a rank ordered plurality of first control signals in response to the Y bit number;
• at least (Y/2) rank ordered rows of (X+2) rank ordered multiplexing means, said multiplexing means forming (X+Y) rank ordered column, wherein said first row includes multiplexing means forming columns of rank 1 to (X+2), said (Y/2)th row includes multiplexing means forming columns of rank (Y-1) to (X+Y), the remaining rows of multiplexing means, if any, having multiplexing means each of which is included in a predetermined column and the first multiplexing means of each remaining row having a column rank which is two ranks greater than the first multiplexing means of the row of immediately lower rank, the first of the (X+2) multiplexing means of each row coupling either a predetermined logic level or the least significant bit of the X bit number to a multiplexer output thereof in response to a predetermined one of the first control signals, the (X+2)nd of the multiplexing means of each row coupling a sign mode control signal to a multiplexer output thereof in response to a predetermined one of the first control signals, and the remainder of the multiplexing means of each row coupling a predetermined one of two predetermined bits of the X bit number to a multiplexer output thereof, in response to the first control signals;
• at least (Y/2) rank ordered rows of adder means, including:
• [(Y/2)-2] rows of (X+1) adders, each of said (X+1) adders having a predetermined column rank and an output sum propagation delay which is substantially twice an output carry delay thereof, each of said adders having at least two inputs, each input adapted for receiving either a predetermined one of the (X+Y) bits of the input number, a partial product bit or an output from a predetermined one of said multiplexing means, each of said adders of the ranked [(Y/2)-2] rows except the highest ranked row having a sum output for providing a partial product sum of predetermined column rank which is coupled to an adder input of an adder having the same column rank and a row rank at least two ranks greater, and a carry output for providing a carry input signal to an adder input of an adder having a column rank one rank greater and a row rank at least one rank greater, each of said adders of the highest ranked row having a sum output and a carry output, said sum output providing a sum input to an adder having the same column rank and a row rank at least one rank greater, and said carry output providing a carry input signal to an adder having a column rank and a row rank one rank greater;
• one row of (X+Y-4) adders of next to greatest row rank, each of said (X+Y-4) adders having a predetermined column rank and three inputs, each input adapted for receiving an input bit representing either a partial product bit, an output from a predetermined one of the multiplexing means, or a bit of the input number;
• and
• one row of (X+Y) carry propagate adders of greatest row rank, each of said (X+Y) adders having a predetermined column rank and three inputs, each input receiving a predetermined one of either a sum input bit, a carry input bit, an output bit from a predetermined one of the multiplexing means, a predetermined bit of the input number, a carry bit from the carry propagate adder of immediately lower column rank, if any, or a predetermined one of the first control signals, each of said carry propagate adders providing a predetermined bit of the accumulated product.

An X.times.Y bit array multiplier circuit for providing a product of an X bit number and a Y bit number, where X and Y are integers, comprising:

• encoding means for implementing a predetermined algorithm and providing a rank ordered plurality of first control signals in response to the Y bit number;
• a rank ordered plurality of multiplexer means forming at least (Y/2) rank ordered rows and (X+Y) rank ordered columns, each of the multiplexer means having a plurality of control inputs, each control input being coupled to a predetermined one of the rank ordered first control signals, for coupling a predetermined one of the rank ordered first control signals, for coupling a predetermined one of a plurality of input bits of the X bit number of predetermined bit weight to an output;
• and
• a rank ordered plurality of adder means forming at least [(Y/2)-1] rank ordered rows, each of said adder means having a predetermined column rank within said (X+Y) columns, the highest ranked row of the adder means providing a product output number, all remaining rows providing output sum and carry bits of predetermined bit weight, each adder means of the remaining rows providing a partial product output sum bit of predetermined bit weight which is coupled to an input of an adder means having a higher row rank and the same column rank, at least one row of said adder means having each partial product output sum bit thereof coupled to an adder input of adder means of corresponding column rank and at least two row ranks greater.