Performance power optimized full adder
AssigneeQUALCOMM Incorporated
InventorsManish Srivastava, Esakkimuthu Dhakshinamoorthy, Neha Gupta
Life of this patent
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Abstract
A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.
Claims11
A sum logic circuit for a full adder for adding a first input signal, a second input signal, and a carry-in signal, the sum logic circuit comprising:
- an exclusive not-OR (XNOR) gate configured to XNOR the first input signal with the second input signal to form an XNOR signal;
- a first inverter configured to invert the XNOR signal to form an exclusive OR (XOR) signal;
- a second inverter configured to invert the carry-in signal to form a complement carry-in signal;
- a first AND gate configured to AND the complement carry-in signal and the XNOR signal to form a first AND signal;
- a second AND gate configured to AND the carry-in signal and the XOR signal to form a second AND signal;
- and
- a not-OR (NOR) gate configured to NOR the first AND signal and the second AND signal to form a sum signal.
A sum logic circuit for a full adder for adding a first input signal, a second input signal, and a carry-in signal to form a sum signal, the sum logic circuit comprising:
- an exclusive not-OR (XNOR) gate configured to XNOR the first input signal with the second input signal to form an XNOR signal;
- a first inverter configured to invert the XNOR signal to form an exclusive OR (XOR) signal;
- a second inverter configured to invert the carry-in signal to form a complement carry-in signal;
- a plurality of logic gates configured to process the carry-in signal, the complement carry-in signal, the XNOR signal, and the XOR signal to produce a sum signal on a sum node;
- the plurality of logic gates comprising a first switch coupled between the sum signal node and a power supply node for carrying a power supply voltage, wherein the first switch is configured to close responsive to the complement carry-in signal and the XOR signal both being discharged.
A method for forming a sum signal for a full adder, comprising:
- exclusive not-ORing (XNORing) a pair of input signals for the full adder in an XNOR gate to form an XNOR signal;
- inverting the XNOR signal in an inverter to form an XOR signal;
- ANDing the complement of the carry-in signal and the XNOR signal in a first AND gate to form a first AND output signal;
- ANDing the carry-in signal and the XOR signal in a second AND gate to form a second AND output signal;
- and
- not-ORing the first AND output signal and the second AND output signal in a NOR gate to form the sum signal.
Dependencies are inferred from the claim text.