Ultra-high speed full adder (fa) and carry generator circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsMitesh Goyal, Somya Agarwal, Mayuresh Dhanawade, Abhishek Ghosh, Akash Singh
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Abstract
A Full Adder (FA) circuit may include a Sum Generation (SG) circuit configured to: generate at least one of an XNOR signal or an XOR signal using at least one of a first NOR signal, an AND signal, a NAND signal, and an OR signal; and generate an output SUM signal using the generated at least one of the XN signal and the X signal. The FA circuit may further include a Carry Output Generation (COG) circuit connected to the SG circuit to generate a CO signal using the first NOR signal, the AND signal, the NAND signal, and/or the OR signal.
Claims27
A Full Adder (FA) circuit, comprising:
- a Sum Generation (SG) circuit configured to:
- generate at least one of an XNOR (“XN”) signal, and an XOR (“X”) signal using at least one of a first NOR signal, an AND signal, a NAND signal, and an OR signal;
- and
- generate an output SUM signal using the generated at least one of the XN signal, and the X signal;
- and
- a Carry Output Generation (COG) circuit connected to the SG circuit and configured to generate a Carry Output (CO) signal using the at least one of the first NOR signal, the AND signal, the NAND signal, or the OR signal.
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Dependencies are inferred from the claim text.