Functionally complete family of self-timed dynamic logic circuits

A logic gate for use in a logic system having a plurality of vector logic states wherein one and only one vector logic state is defined valid by a high logic state on a predetermined exclusive set of one or more logic paths and wherein an invalid vector logic state is defined where all said logic paths exhibit a low logic state, the logic gate comprising:

• logic means for receiving vector inputs, for performing logic functions upon said vector inputs, and for providing a first vector output;
• buffer means for receiving said first vector output, for maintaining a second vector output of said logic gate at said invalid state before receiving said first vector output, and for providing said second vector output in a valid vector logic state after receiving said first vector output, said buffer means comprising a static CMOSFET inverter having a p-channel MOSFET and an n-channel MOSFET, said p-channel MOSFET having a wider gate than said n-channel MOSFET;
• and
• arming means for periodically precharging said buffer means to maintain said second vector output at said invalid state.

A self-timed dynamic logic system, comprising:

• n-cascaded logic gates, each of said n cascaded logic gates having logic for receiving logic inputs on a plurality of logic paths, an inverting buffer connected to said logic, said inverting buffer for providing a buffer output, said buffer output triggered from a low logic state to a high logic state by said logic, and an arming mechanism adapted to periodically precharge a buffer input of said inverting buffer to thereby cause said inverting buffer to maintain said buffer output at a low logic state until triggered by said logic;
• m precharge facilitating means, each of said m precharge facilitating means connected to said logic of one of said n cascaded logic gates, said m precharge facilitating means for disabling said logics of said n cascaded logic gates during said precharge and for promoting parallel precharging of said n cascaded logic gates;
• and
• wherein the ratio of m to n is less than one to one.

A logic gate for a self-timed and monotonic logic system utilizing vector logic states, each of said vector logic states defined by any number of binary logic states situated respectively on a plurality of logic paths, each of said vector logic states encoding timing information by defining an invalid state when all said binary logic states concurrently exhibit a logic low and by defining one of a plurality of valid states when a preselected exclusive subset of said binary logic states exhibits a logic high, the logic gate for deriving a vector output from a plurality of vector inputs, comprising:

• ladder logic means comprising a plurality of ladder logics, said ladder logic means for receiving said vector inputs, for performing logic functions upon said vector inputs, and for providing a ladder logic output from a ladder logic;
• buffer means comprising a plurality of inverting buffers associated respectively with said ladder logics, said inverting buffers configured to output said binary logic states defining said vector output, said inverting buffers configured to maintain said binary logic states at a logic low before receiving said ladder logic output so that said vector output exhibits said invalid state, one of said inverting buffers configured to receive said ladder logic output and invert said ladder logic output to thereby derive said vector output in a valid state;
• said buffer means comprising a static CMOSFET inverter having a p-channel MOSFET and an n-channel MOSFET, said p-channel MOSFET having a wider gate than said n-channel MOSFET;
• and
• arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffers, said arming mechanisms configured to periodically precharge said buffer mechanisms respectively to thereby cause said buffer mechanisms to maintain said binary logic states at said logic low.