Performance power optimized full adder
AssigneeQUALCOMM Incorporated
InventorsManish SRIVASTAVA, Esakkimuthu DHAKSHINAMOORTHY, Neha GUPTA
Life of this patent
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Abstract
A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.
Claims20
A carry-out logic circuit for a full adder for adding a first input signal, a second input signal, and a carry-in signal, the carry-out logic circuit comprising:
- a first node for a complement carry-out signal;
- a first switch configured to couple the first node to a power supply node responsive to the first input signal and the second input signal both being discharged;
- a second switch configured to couple the first node to ground responsive to the first input signal and the second input signal both being charged to a power supply voltage;
- a first transistor arranged in parallel with a second transistor, wherein the first transistor is configured to switch on responsive to the first input signal being discharged and wherein the second transistor is configured to switch on responsive to the second input signal being discharged;
- and
- a third transistor arranged in series with the first transistor and the second transistor to form a first series of transistors coupled between the first node and the power supply node, wherein the third transistor is configured to switch on responsive to the carry-in signal being discharged.
A sum logic circuit for a full adder for adding a first input signal, a second input signal, and a carry-in signal, the sum logic circuit comprising:
- an exclusive not-OR (XNOR) gate configured to XNOR the first input signal with the second input signal to form an XNOR signal;
- a first inverter configured to invert the XNOR signal to form an exclusive OR (XOR) signal;
- a second inverter configured to invert the carry-in signal to form a complement carry-in signal;
- and
- a plurality of logic gates configured to process the carry-in signal, the complement carry-in signal, the XNOR signal, and the XOR signal to produce a sum signal.
A method for forming a sum signal for a full adder, comprising:
- exclusive not-ORing (XNORing) a pair of input signals for the full adder to form an XNOR signal;
- inverting the XNOR signal to form an XOR signal;
- and
- processing the XNOR signal, the XOR signal, a carry-in signal, and a complement of the carry-in signal to form the sum signal.
Dependencies are inferred from the claim text.