Memory system and memory die with cascaded calculating circuits

A memory system, comprising:

• a plurality of memory dies stacked within the memory system, each of the memory dies comprising:
• a first numbering circuit configured to generate an output number signal according to an input number signal, the first numbering circuit comprising:
• a first stage calculating circuit and a previous stage calculating circuit coupled in series, wherein a first input end of the first stage calculating circuit is configured to receive a first output bit from the previous stage calculating circuit, and a second input end of the first stage calculating circuit is configured to receive a corresponding bit of a second input number signal generated by a second numbering circuit which is coupled to the second input end of the first stage calculating circuit in first numbering circuit,
• wherein the first stage calculating circuit is configured to generate a second output bit which serves as a correspond bit of the output number signal generated by the first numbering circuit.